Lines Matching refs:d0
242 moveb #MCFINTC2_VECBASE,%d0
243 moveb %d0,0x16b(%a1) /* interrupt base register */
248 movel #0x001F0021,%d0 /* disable C/I bit */
249 movel %d0,0x84(%a0) /* set CSMR0 */
255 movel 0x180(%a1),%d0 /* get current PLL value */
256 andl #0xfffffffe,%d0 /* PLL bypass first */
257 movel %d0,0x180(%a1) /* set PLL register */
266 movel #0x125a40f0,%d0 /* set for 140MHz */
267 movel %d0,0x180(%a1) /* set PLL register */
268 orl #0x1,%d0
269 movel %d0,0x180(%a1) /* set PLL register */
276 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
277 movel %d0,0x8c(%a0)
278 movel #0x001f0021,%d0 /* CS1 size of 1Mb */
279 movel %d0,0x90(%a0)
280 movew #0x0080,%d0 /* CS1 = 16bit port, AA */
281 movew %d0,0x96(%a0)
286 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
287 movel %d0,0x98(%a0)
288 movel #0x001f0001,%d0 /* CS2 size of 1MB */
289 movel %d0,0x9c(%a0)
290 movew #0x0080,%d0 /* CS2 = 16bit, TA */
291 movew %d0,0xa2(%a0)
293 movel #0x00107000,%d0 /* IDEconfig1 */
294 movel %d0,0x18c(%a1)
295 movel #0x000c0400,%d0 /* IDEconfig2 */
296 movel %d0,0x190(%a1)
298 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
299 orl %d0,0xc(%a1) /* function GPIO19 */
300 orl %d0,0x8(%a1) /* enable GPIO19 as output */
301 orl %d0,0x4(%a1) /* de-assert IDE reset */