24 .macro v7m_cache_read, rt, reg
25 	movw	\rt, #:lower16:BASEADDR_V7M_SCB + \reg
26 	movt	\rt, #:upper16:BASEADDR_V7M_SCB + \reg
27 	ldr     \rt, [\rt]
30 .macro v7m_cacheop, rt, tmp, op, c = al
33 	str\c	\rt, [\tmp]
37 .macro	read_ccsidr, rt  argument
38 	v7m_cache_read \rt, V7M_SCB_CCSIDR
41 .macro read_clidr, rt  argument
42 	v7m_cache_read \rt, V7M_SCB_CLIDR
45 .macro	write_csselr, rt, tmp
46 	v7m_cacheop \rt, \tmp, V7M_SCB_CSSELR
52 .macro dcisw, rt, tmp
53 	v7m_cacheop \rt, \tmp, V7M_SCB_DCISW
59 .macro dccisw, rt, tmp
60 	v7m_cacheop \rt, \tmp, V7M_SCB_DCCISW
67 .macro dccimvac\c, rt, tmp
68 	v7m_cacheop \rt, \tmp, V7M_SCB_DCCIMVAC, \c
76 .macro dcimvac\c, rt, tmp
77 	v7m_cacheop \rt, \tmp, V7M_SCB_DCIMVAC, \c
84 .macro dccmvau, rt, tmp
85 	v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAU
91 .macro dccmvac,  rt, tmp
92 	v7m_cacheop \rt, \tmp, V7M_SCB_DCCMVAC
98 .macro icimvau, rt, tmp
99 	v7m_cacheop \rt, \tmp, V7M_SCB_ICIMVAU
106 .macro invalidate_icache, rt  argument
107 	v7m_cacheop \rt, \rt, V7M_SCB_ICIALLU
108 	mov \rt, #0
115 .macro invalidate_bp, rt  argument
116 	v7m_cacheop \rt, \rt, V7M_SCB_BPIALL
117 	mov \rt, #0