Lines Matching refs:ldr
53 ldr \rd, tegra_pll_state
58 ldr \rd, [\r_car_base, #\pll_base]
60 ldr \rd, tegra_pll_state
71 ldr \rd, [\r_car_base, #\pll_base]
79 ldr \rd, [\base, #EMC_ADR_CFG]
117 ldr r3, =TEGRA_FLOW_CTRL_VIRT
120 ldr r2, [r3, r1]
125 ldr r3, =TEGRA_CLK_RESET_VIRT
213 ldr r6, tegra20_sdram_pad_size
215 ldr r7, [r2, r5] @ r7 is the addr in the pad_address
217 ldr r1, [r4, r5]
227 ldr r1, [r7]
232 ldr r4, [r4]
238 ldr r1, [r0, #EMC_CFG]
251 ldr r2, [r0, #EMC_EMC_STATUS]
259 ldr r0, [r0, #PMC_SCRATCH41]
294 ldr r1, [r7]
303 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
306 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
309 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
335 ldr r0, [r6, r1] /* memory barrier */
357 ldr r2, [r1, #EMC_EMC_STATUS]
367 ldr r3, [r1, #EMC_EMC_STATUS]
377 ldr r6, tegra20_sdram_pad_size
379 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
381 ldr r1, [r0]
384 ldr r1, [r3, r5]
393 ldr r0, [r5, #CLK_RESET_SCLK_BURST]