Lines Matching refs:ldr

69 	ldr	r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
74 	ldr	r1, get_l2cache_base
87 	ldr	r1, kernel_flush
104 	ldr	r1, kernel_flush
120 	ldr	r3, [r4, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
123 	ldr	r0, [r2, #L2X0_AUX_CTRL]
125 	ldr	r0, [r2, #L310_PREFETCH_CTRL]
128 	ldr	r0, l2_val
131 	ldr	r0, [r2, #L2X0_CLEAN_INV_WAY]
132 	ldr	r1, l2_val
148 	ldr	r0, [r2, #L2X0_CACHE_SYNC]
155 	ldr	r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
156 	ldr	r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
169 	ldr	r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET]
170 	ldr	r0, [r1]
179 	ldr     r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
187 	ldr     r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
196 	ldr	r1, am43xx_virt_emif_clkctrl
197 	ldr	r2, [r1]
202 	ldr	r2, [r1]
212 	ldr	r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET]
214 	ldr	r0, [r1, #RTC_PMIC_REG]
220 	ldr	r0, [r1, #RTC_PMIC_REG]
223 	ldr	r2, [r1, #RTC_SECONDS_REG]
225 	ldr	r0, [r1, #RTC_SECONDS_REG]
244 	ldr	r1, am43xx_virt_mpu_clkctrl
245 	ldr	r2, [r1]
252 	ldr	r1, am43xx_virt_mpu_clkstctrl
292 	ldr	r1, am43xx_virt_mpu_clkstctrl
297 	ldr	r1, am43xx_virt_mpu_clkctrl
303 	ldr	r1, am43xx_virt_emif_clkctrl
307 	ldr	r3, [r1]
328 	ldr	r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
343 	ldr	r1, am43xx_virt_mpu_clkstctrl
348 	ldr	r2, am43xx_phys_emif_poweroff
353 	ldr	r1, am43xx_phys_emif_clkctrl
357 	ldr	r3, [r1]
363 	ldr     r1, [r9, #EMIF_PM_RESTORE_CONTEXT_OFFSET]
366 	ldr     r1, [r9, #EMIF_PM_EXIT_SR_OFFSET]
369 	ldr     r2, am43xx_phys_emif_poweroff
373 	ldr     r1, [r9, #EMIF_PM_RUN_HW_LEVELING]
377 	ldr	r2, l2_cache_base
378 	ldr	r0, [r2, #L2X0_CTRL]
384 	ldr	r3, [r4, #AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET]
385 	ldr     r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET]
387 	ldr	r12, l2_smc1
392 	ldr     r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET]
393 	ldr	r12, l2_smc2
399 	ldr	r0, l2_val
400 	ldr	r2, l2_cache_base
403 	ldr	r0, [r2, #L2X0_INV_WAY]
404 	ldr	r1, l2_val
415 	ldr	r2, l2_cache_base
419 	ldr	r0, [r2, #L2X0_CACHE_SYNC]
424 	ldr	r12, l2_smc3
432 	ldr	pc, resume_addr