Lines Matching refs:clk
47 unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate) in omap1_uart_recalc() argument
49 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
50 return val & 1 << clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
53 unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate) in omap1_sossi_recalc() argument
63 static void omap1_clk_allow_idle(struct omap1_clk *clk) in omap1_clk_allow_idle() argument
65 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; in omap1_clk_allow_idle()
67 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_allow_idle()
74 static void omap1_clk_deny_idle(struct omap1_clk *clk) in omap1_clk_deny_idle() argument
76 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; in omap1_clk_deny_idle()
78 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_deny_idle()
166 unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate) in omap1_ckctl_recalc() argument
169 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc()
172 clk->rate = p_rate / dsor; in omap1_ckctl_recalc()
173 return clk->rate; in omap1_ckctl_recalc()
178 struct omap1_clk *clk = to_omap1_clk(hw); in omap1_clk_is_enabled() local
183 if (!clk->ops) /* no gate -- always enabled */ in omap1_clk_is_enabled()
186 if (clk->ops == &clkops_dspck) { in omap1_clk_is_enabled()
193 if (clk->flags & ENABLE_REG_32BIT) in omap1_clk_is_enabled()
194 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_is_enabled()
196 regval32 = __raw_readw(clk->enable_reg); in omap1_clk_is_enabled()
198 ret = regval32 & (1 << clk->enable_bit); in omap1_clk_is_enabled()
207 unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate) in omap1_ckctl_recalc_dsp_domain() argument
222 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc_dsp_domain()
230 int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) in omap1_select_table_rate() argument
265 int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) in omap1_clk_set_rate_dsp_domain() argument
277 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_dsp_domain()
278 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_dsp_domain()
280 clk->rate = p_rate / (1 << dsor_exp); in omap1_clk_set_rate_dsp_domain()
285 long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, in omap1_clk_round_rate_ckctl_arm() argument
297 int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) in omap1_clk_set_rate_ckctl_arm() argument
313 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_ckctl_arm()
314 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_ckctl_arm()
317 clk->rate = p_rate / (1 << dsor_exp); in omap1_clk_set_rate_ckctl_arm()
324 long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) in omap1_round_to_table_rate() argument
375 long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) in omap1_round_uart_rate() argument
380 int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) in omap1_set_uart_rate() argument
388 val = 1 << clk->enable_bit; in omap1_set_uart_rate()
395 val |= __raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit); in omap1_set_uart_rate()
396 __raw_writel(val, clk->enable_reg); in omap1_set_uart_rate()
400 clk->rate = rate; in omap1_set_uart_rate()
406 int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) in omap1_set_ext_clk_rate() argument
413 clk->rate = 96000000 / dsor; in omap1_set_ext_clk_rate()
422 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; in omap1_set_ext_clk_rate()
423 __raw_writew(ratio_bits, clk->enable_reg); in omap1_set_ext_clk_rate()
440 long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) in omap1_round_sossi_rate() argument
453 int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate) in omap1_set_sossi_rate() argument
471 clk->rate = p_rate / (div + 1); in omap1_set_sossi_rate()
478 long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate) in omap1_round_ext_clk_rate() argument
483 int omap1_init_ext_clk(struct omap1_clk *clk) in omap1_init_ext_clk() argument
489 ratio_bits = __raw_readw(clk->enable_reg) & ~1; in omap1_init_ext_clk()
490 __raw_writew(ratio_bits, clk->enable_reg); in omap1_init_ext_clk()
498 clk-> rate = 96000000 / dsor; in omap1_init_ext_clk()
505 struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw)); in omap1_clk_enable() local
508 if (parent && clk->flags & CLOCK_NO_IDLE_PARENT) in omap1_clk_enable()
511 if (clk->ops && !(WARN_ON(!clk->ops->enable))) in omap1_clk_enable()
512 ret = clk->ops->enable(clk); in omap1_clk_enable()
519 struct omap1_clk *clk = to_omap1_clk(hw), *parent = to_omap1_clk(clk_hw_get_parent(hw)); in omap1_clk_disable() local
521 if (clk->ops && !(WARN_ON(!clk->ops->disable))) in omap1_clk_disable()
522 clk->ops->disable(clk); in omap1_clk_disable()
524 if (likely(parent) && clk->flags & CLOCK_NO_IDLE_PARENT) in omap1_clk_disable()
528 static int omap1_clk_enable_generic(struct omap1_clk *clk) in omap1_clk_enable_generic() argument
534 if (unlikely(clk->enable_reg == NULL)) { in omap1_clk_enable_generic()
536 clk_hw_get_name(&clk->hw)); in omap1_clk_enable_generic()
541 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_enable_generic()
543 else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) in omap1_clk_enable_generic()
545 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) in omap1_clk_enable_generic()
547 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) in omap1_clk_enable_generic()
549 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_enable_generic()
552 if (clk->flags & ENABLE_REG_32BIT) { in omap1_clk_enable_generic()
553 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_enable_generic()
554 regval32 |= (1 << clk->enable_bit); in omap1_clk_enable_generic()
555 __raw_writel(regval32, clk->enable_reg); in omap1_clk_enable_generic()
557 regval16 = __raw_readw(clk->enable_reg); in omap1_clk_enable_generic()
558 regval16 |= (1 << clk->enable_bit); in omap1_clk_enable_generic()
559 __raw_writew(regval16, clk->enable_reg); in omap1_clk_enable_generic()
562 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_enable_generic()
564 else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) in omap1_clk_enable_generic()
566 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) in omap1_clk_enable_generic()
568 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) in omap1_clk_enable_generic()
570 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_enable_generic()
576 static void omap1_clk_disable_generic(struct omap1_clk *clk) in omap1_clk_disable_generic() argument
582 if (clk->enable_reg == NULL) in omap1_clk_disable_generic()
586 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_disable_generic()
588 else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) in omap1_clk_disable_generic()
590 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) in omap1_clk_disable_generic()
592 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) in omap1_clk_disable_generic()
594 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_disable_generic()
597 if (clk->flags & ENABLE_REG_32BIT) { in omap1_clk_disable_generic()
598 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_disable_generic()
599 regval32 &= ~(1 << clk->enable_bit); in omap1_clk_disable_generic()
600 __raw_writel(regval32, clk->enable_reg); in omap1_clk_disable_generic()
602 regval16 = __raw_readw(clk->enable_reg); in omap1_clk_disable_generic()
603 regval16 &= ~(1 << clk->enable_bit); in omap1_clk_disable_generic()
604 __raw_writew(regval16, clk->enable_reg); in omap1_clk_disable_generic()
607 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_disable_generic()
609 else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) in omap1_clk_disable_generic()
611 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) in omap1_clk_disable_generic()
613 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) in omap1_clk_disable_generic()
615 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_disable_generic()
624 static int omap1_clk_enable_dsp_domain(struct omap1_clk *clk) in omap1_clk_enable_dsp_domain() argument
634 retval = omap1_clk_enable_generic(clk); in omap1_clk_enable_dsp_domain()
643 static void omap1_clk_disable_dsp_domain(struct omap1_clk *clk) in omap1_clk_disable_dsp_domain() argument
652 omap1_clk_disable_generic(clk); in omap1_clk_disable_dsp_domain()
664 static int omap1_clk_enable_uart_functional_16xx(struct omap1_clk *clk) in omap1_clk_enable_uart_functional_16xx() argument
669 ret = omap1_clk_enable_generic(clk); in omap1_clk_enable_uart_functional_16xx()
672 uclk = (struct uart_clk *)clk; in omap1_clk_enable_uart_functional_16xx()
681 static void omap1_clk_disable_uart_functional_16xx(struct omap1_clk *clk) in omap1_clk_disable_uart_functional_16xx() argument
686 uclk = (struct uart_clk *)clk; in omap1_clk_disable_uart_functional_16xx()
689 omap1_clk_disable_generic(clk); in omap1_clk_disable_uart_functional_16xx()
700 struct omap1_clk *clk = to_omap1_clk(hw); in omap1_clk_recalc_rate() local
702 if (clk->recalc) in omap1_clk_recalc_rate()
703 return clk->recalc(clk, p_rate); in omap1_clk_recalc_rate()
705 return clk->rate; in omap1_clk_recalc_rate()
710 struct omap1_clk *clk = to_omap1_clk(hw); in omap1_clk_round_rate() local
712 if (clk->round_rate != NULL) in omap1_clk_round_rate()
713 return clk->round_rate(clk, rate, p_rate); in omap1_clk_round_rate()
720 struct omap1_clk *clk = to_omap1_clk(hw); in omap1_clk_set_rate() local
723 if (clk->set_rate) in omap1_clk_set_rate()
724 ret = clk->set_rate(clk, rate, p_rate); in omap1_clk_set_rate()
734 struct omap1_clk *clk = to_omap1_clk(hw); in omap1_clk_init_op() local
736 if (clk->init) in omap1_clk_init_op()
737 return clk->init(clk); in omap1_clk_init_op()
746 struct omap1_clk *clk = to_omap1_clk(hw); in omap1_clk_disable_unused() local
751 if (clk->enable_reg == DSP_IDLECT2) { in omap1_clk_disable_unused()
797 unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate) in followparent_recalc() argument
806 unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate) in omap_fixed_divisor_recalc() argument
808 WARN_ON(!clk->fixed_div); in omap_fixed_divisor_recalc()
810 return p_rate / clk->fixed_div; in omap_fixed_divisor_recalc()
816 struct clk *clkp; in propagate_rate()