Lines Matching refs:ldr
42 2: ldr r8, [pmc, #AT91_PMC_SR]
54 1: ldr r7, [pmc, #AT91_PMC_SR]
65 1: ldr r7, [pmc, #AT91_PMC_SR]
99 ldr r7, .sfrbu
101 ldr r9, [r7, #AT91_SFRBU_25LDOCR]
107 ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
130 ldr r2, .sramc_base
131 ldr r3, .sramc_phy_base
132 ldr r7, .pm_mode
137 ldr tmp1, [r2, #UDDRC_PCTRL_0]
141 ldr tmp1, [r2, #UDDRC_PCTRL_1]
145 ldr tmp1, [r2, #UDDRC_PCTRL_2]
149 ldr tmp1, [r2, #UDDRC_PCTRL_3]
153 ldr tmp1, [r2, #UDDRC_PCTRL_4]
159 ldr tmp1, [r2, #UDDRC_PSTAT]
160 ldr tmp2, =UDDRC_PSTAT_ALL_PORTS
165 ldr tmp1, [r2, #UDDRC_PWRCTL]
171 ldr tmp1, [r2, #UDDRC_STAT]
181 ldr tmp1, [r3, DDR3PHY_ACDLLCR]
186 ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
190 ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
196 ldr tmp1, [r3, #DDR3PHY_DXCCR]
201 ldr tmp1, [r3, #DDR3PHY_ACIOCR]
208 ldr tmp1, [r3, #DDR3PHY_DSGCR]
219 ldr r2, .sramc_base
220 ldr r3, .sramc_phy_base
223 ldr tmp1, [r3, #DDR3PHY_DXCCR]
228 ldr tmp1, [r3, #DDR3PHY_ACIOCR]
235 ldr tmp1, [r3, #DDR3PHY_DSGCR]
240 ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
244 ldr tmp1, [r3, #DDR3PHY_DX1DLLCR]
253 ldr tmp1, [r2, #UDDRC_DFIMISC]
262 ldr tmp1, [r2, #UDDRC_SWSTAT]
273 ldr tmp1, [r3, #DDR3PHY_PGSR]
282 ldr tmp1, [r2, #UDDRC_DFIMISC]
292 ldr tmp1, [r2, #UDDRC_SWSTAT]
297 ldr tmp1, [r2, #UDDRC_PWRCTL]
303 ldr tmp1, [r2, #UDDRC_STAT]
309 ldr tmp1, [r2, #UDDRC_PCTRL_0]
313 ldr tmp1, [r2, #UDDRC_PCTRL_1]
317 ldr tmp1, [r2, #UDDRC_PCTRL_2]
321 ldr tmp1, [r2, #UDDRC_PCTRL_3]
325 ldr tmp1, [r2, #UDDRC_PCTRL_4]
341 ldr r1, .memtype
342 ldr r2, .sramc_base
361 ldr r3, [r2, #AT91_DDRSDRC_MDR]
371 ldr r3, [r2, #AT91_DDRSDRC_LPR]
378 ldr r2, .sramc1_base
382 ldr r3, [r2, #AT91_DDRSDRC_MDR]
392 ldr r3, [r2, #AT91_DDRSDRC_LPR]
406 ldr r3, [r2, #AT91_SDRAMC_LPR]
412 ldr r3, .saved_sam9_lpr
427 ldr r1, .memtype
428 ldr r2, .sramc_base
450 ldr r3, .saved_sam9_mdr
453 ldr r3, .saved_sam9_lpr
457 ldr r2, .sramc1_base
468 ldr r3, .saved_sam9_lpr
476 ldr pmc, .pmc_base
477 ldr tmp2, .pm_mode
478 ldr tmp3, .mckr_offset
485 ldr tmp1, [pmc, tmp3]
496 ldr tmp1, [pmc, #AT91_CKGR_MOR]
502 ldr tmp1, [pmc, #AT91_PMC_SR]
508 ldr tmp1, [pmc, #AT91_CKGR_MOR]
515 2: ldr tmp1, [pmc, #AT91_PMC_SR]
527 ldr tmp3, .mckr_offset
528 ldr tmp1, [pmc, tmp3]
537 ldr tmp1, .saved_osc_status
542 ldr tmp1, [pmc, #AT91_CKGR_MOR]
549 3: ldr tmp1, [pmc, #AT91_PMC_SR]
554 4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
568 ldr pmc, .pmc_base
569 ldr tmp2, .mckr_offset
573 ldr tmp1, [pmc, #AT91_PMC_SR]
579 ldr tmp1, [pmc, #AT91_CKGR_MOR]
586 1: ldr tmp1, [pmc, #AT91_PMC_SR]
591 2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
600 ldr tmp1, [pmc, #AT91_CKGR_MOR]
607 ldr tmp1, [pmc, tmp2]
615 ldr tmp1, [pmc, #AT91_CKGR_MOR]
628 ldr tmp1, [pmc, #AT91_CKGR_MOR]
637 ldr tmp1, [pmc, tmp2]
644 ldr tmp1, [pmc, #AT91_CKGR_MOR]
653 ldr tmp1, [pmc, tmp2]
661 ldr tmp1, .saved_osc_status
666 ldr tmp1, [pmc, #AT91_CKGR_MOR]
673 4: ldr tmp1, [pmc, #AT91_PMC_SR]
682 ldr tmp1, .pmc_version
688 ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT]
694 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
699 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1]
705 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
711 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
717 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
723 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
728 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
737 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
748 ldr tmp2, .saved_pllar
749 ldr tmp3, .pmc_version
755 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
761 ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
765 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1]
772 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
778 ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0]
789 ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT]
795 3: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0]
810 1: ldr tmp1, [pmc, #AT91_PMC_SR]
823 ldr pmc, .pmc_base
832 ldr tmp2, [pmc, #AT91_PMC_MCR_V2]
879 ldr pmc, .pmc_base
889 ldr tmp2, .saved_mck1
895 ldr tmp2, .saved_mck2
901 ldr tmp2, .saved_mck3
905 ldr tmp2, .saved_mck4
910 ldr tmp3, [pmc, #AT91_PMC_MCR_V2]
932 ldr pmc, .pmc_base
933 ldr tmp2, .mckr_offset
934 ldr tmp3, .pm_mode
937 ldr tmp1, [pmc, tmp2]
960 ldr tmp3, .pm_mode
975 ldr pmc, .pmc_base
982 ldr tmp1, .mckr_offset
983 ldr tmp2, .saved_mckr
994 ldr pmc, .pmc_base
995 ldr tmp2, .mckr_offset
996 ldr tmp1, [pmc, tmp2]
1004 ldr r0, .sfrbu
1009 1: ldr tmp1, [r0, #0x10]
1014 ldr r0, .shdwc
1040 ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]
1042 ldr tmp1, [r0, #PM_DATA_PMC_VERSION]
1044 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
1046 ldr tmp1, [r0, #PM_DATA_MODE]
1053 ldr tmp1, [r0, #PM_DATA_PMC]
1058 ldr tmp1, [r0, #PM_DATA_RAMC0]
1063 ldr tmp1, [r0, #PM_DATA_RAMC1]
1070 ldr tmp1, [r0, #PM_DATA_RAMC_PHY]
1075 ldr tmp1, [r0, #PM_DATA_SHDWC]
1080 ldr tmp1, [r0, #PM_DATA_SFRBU]
1089 ldr r0, .pm_mode
1100 ldr pmc, .pmc_base