Lines Matching refs:clock
3 * Device Tree Source for DRA7xx clock data
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
23 #clock-cells = <0>;
24 compatible = "ti,dra7-atl-clock";
25 clock-output-names = "atl_clkin2_ck";
29 atl_clkin3_ck: clock-atl-clkin3 {
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
32 clock-output-names = "atl_clkin3_ck";
36 hdmi_clkin_ck: clock-hdmi-clkin {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-output-names = "hdmi_clkin_ck";
40 clock-frequency = <0>;
43 mlb_clkin_ck: clock-mlb-clkin {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-output-names = "mlb_clkin_ck";
47 clock-frequency = <0>;
50 mlbp_clkin_ck: clock-mlbp-clkin {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-output-names = "mlbp_clkin_ck";
54 clock-frequency = <0>;
57 pciesref_acs_clk_ck: clock-pciesref-acs {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-output-names = "pciesref_acs_clk_ck";
61 clock-frequency = <100000000>;
64 ref_clkin0_ck: clock-ref-clkin0 {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-output-names = "ref_clkin0_ck";
68 clock-frequency = <0>;
71 ref_clkin1_ck: clock-ref-clkin1 {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-output-names = "ref_clkin1_ck";
75 clock-frequency = <0>;
78 ref_clkin2_ck: clock-ref-clkin2 {
79 #clock-cells = <0>;
80 compatible = "fixed-clock";
81 clock-output-names = "ref_clkin2_ck";
82 clock-frequency = <0>;
85 ref_clkin3_ck: clock-ref-clkin3 {
86 #clock-cells = <0>;
87 compatible = "fixed-clock";
88 clock-output-names = "ref_clkin3_ck";
89 clock-frequency = <0>;
92 rmii_clk_ck: clock-rmii {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 clock-output-names = "rmii_clk_ck";
96 clock-frequency = <0>;
99 sdvenc_clkin_ck: clock-sdvenc-clkin {
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 clock-output-names = "sdvenc_clkin_ck";
103 clock-frequency = <0>;
106 secure_32k_clk_src_ck: clock-secure-32k-clk-src {
107 #clock-cells = <0>;
108 compatible = "fixed-clock";
109 clock-output-names = "secure_32k_clk_src_ck";
110 clock-frequency = <32768>;
113 sys_clk32_crystal_ck: clock-sys-clk32-crystal {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-output-names = "sys_clk32_crystal_ck";
117 clock-frequency = <32768>;
120 sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
121 #clock-cells = <0>;
122 compatible = "fixed-factor-clock";
123 clock-output-names = "sys_clk32_pseudo_ck";
125 clock-mult = <1>;
126 clock-div = <610>;
129 virt_12000000_ck: clock-virt-12000000 {
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
132 clock-output-names = "virt_12000000_ck";
133 clock-frequency = <12000000>;
136 virt_13000000_ck: clock-virt-13000000 {
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 clock-output-names = "virt_13000000_ck";
140 clock-frequency = <13000000>;
143 virt_16800000_ck: clock-virt-16800000 {
144 #clock-cells = <0>;
145 compatible = "fixed-clock";
146 clock-output-names = "virt_16800000_ck";
147 clock-frequency = <16800000>;
150 virt_19200000_ck: clock-virt-19200000 {
151 #clock-cells = <0>;
152 compatible = "fixed-clock";
153 clock-output-names = "virt_19200000_ck";
154 clock-frequency = <19200000>;
157 virt_20000000_ck: clock-virt-20000000 {
158 #clock-cells = <0>;
159 compatible = "fixed-clock";
160 clock-output-names = "virt_20000000_ck";
161 clock-frequency = <20000000>;
164 virt_26000000_ck: clock-virt-26000000 {
165 #clock-cells = <0>;
166 compatible = "fixed-clock";
167 clock-output-names = "virt_26000000_ck";
168 clock-frequency = <26000000>;
171 virt_27000000_ck: clock-virt-27000000 {
172 #clock-cells = <0>;
173 compatible = "fixed-clock";
174 clock-output-names = "virt_27000000_ck";
175 clock-frequency = <27000000>;
178 virt_38400000_ck: clock-virt-38400000 {
179 #clock-cells = <0>;
180 compatible = "fixed-clock";
181 clock-output-names = "virt_38400000_ck";
182 clock-frequency = <38400000>;
185 sys_clkin2: clock-sys-clkin2 {
186 #clock-cells = <0>;
187 compatible = "fixed-clock";
188 clock-output-names = "sys_clkin2";
189 clock-frequency = <22579200>;
192 usb_otg_clkin_ck: clock-usb-otg-clkin {
193 #clock-cells = <0>;
194 compatible = "fixed-clock";
195 clock-output-names = "usb_otg_clkin_ck";
196 clock-frequency = <0>;
199 video1_clkin_ck: clock-video1-clkin {
200 #clock-cells = <0>;
201 compatible = "fixed-clock";
202 clock-output-names = "video1_clkin_ck";
203 clock-frequency = <0>;
206 video1_m2_clkin_ck: clock-video1-m2-clkin {
207 #clock-cells = <0>;
208 compatible = "fixed-clock";
209 clock-output-names = "video1_m2_clkin_ck";
210 clock-frequency = <0>;
213 video2_clkin_ck: clock-video2-clkin {
214 #clock-cells = <0>;
215 compatible = "fixed-clock";
216 clock-output-names = "video2_clkin_ck";
217 clock-frequency = <0>;
220 video2_m2_clkin_ck: clock-video2-m2-clkin {
221 #clock-cells = <0>;
222 compatible = "fixed-clock";
223 clock-output-names = "video2_m2_clkin_ck";
224 clock-frequency = <0>;
227 dpll_abe_ck: clock@1e0 {
228 #clock-cells = <0>;
229 compatible = "ti,omap4-dpll-m4xen-clock";
230 clock-output-names = "dpll_abe_ck";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
236 #clock-cells = <0>;
237 compatible = "ti,omap4-dpll-x2-clock";
238 clock-output-names = "dpll_abe_x2_ck";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
243 #clock-cells = <0>;
244 compatible = "ti,divider-clock";
245 clock-output-names = "dpll_abe_m2x2_ck";
254 abe_clk: clock-abe@108 {
255 #clock-cells = <0>;
256 compatible = "ti,divider-clock";
257 clock-output-names = "abe_clk";
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
265 #clock-cells = <0>;
266 compatible = "ti,divider-clock";
267 clock-output-names = "dpll_abe_m2_ck";
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
277 #clock-cells = <0>;
278 compatible = "ti,divider-clock";
279 clock-output-names = "dpll_abe_m3x2_ck";
288 dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
289 #clock-cells = <0>;
290 compatible = "ti,mux-clock";
291 clock-output-names = "dpll_core_byp_mux";
297 dpll_core_ck: clock@120 {
298 #clock-cells = <0>;
299 compatible = "ti,omap4-dpll-core-clock";
300 clock-output-names = "dpll_core_ck";
305 dpll_core_x2_ck: clock-dpll-core-x2 {
306 #clock-cells = <0>;
307 compatible = "ti,omap4-dpll-x2-clock";
308 clock-output-names = "dpll_core_x2_ck";
312 dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
313 #clock-cells = <0>;
314 compatible = "ti,divider-clock";
315 clock-output-names = "dpll_core_h12x2_ck";
324 mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
325 #clock-cells = <0>;
326 compatible = "fixed-factor-clock";
327 clock-output-names = "mpu_dpll_hs_clk_div";
329 clock-mult = <1>;
330 clock-div = <1>;
333 dpll_mpu_ck: clock@160 {
334 #clock-cells = <0>;
335 compatible = "ti,omap5-mpu-dpll-clock";
336 clock-output-names = "dpll_mpu_ck";
341 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
342 #clock-cells = <0>;
343 compatible = "ti,divider-clock";
344 clock-output-names = "dpll_mpu_m2_ck";
353 mpu_dclk_div: clock-mpu-dclk-div {
354 #clock-cells = <0>;
355 compatible = "fixed-factor-clock";
356 clock-output-names = "mpu_dclk_div";
358 clock-mult = <1>;
359 clock-div = <1>;
362 dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
363 #clock-cells = <0>;
364 compatible = "fixed-factor-clock";
365 clock-output-names = "dsp_dpll_hs_clk_div";
367 clock-mult = <1>;
368 clock-div = <1>;
371 dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
372 #clock-cells = <0>;
373 compatible = "ti,mux-clock";
374 clock-output-names = "dpll_dsp_byp_mux";
380 dpll_dsp_ck: clock@234 {
381 #clock-cells = <0>;
382 compatible = "ti,omap4-dpll-clock";
383 clock-output-names = "dpll_dsp_ck";
387 assigned-clock-rates = <600000000>;
390 dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
391 #clock-cells = <0>;
392 compatible = "ti,divider-clock";
393 clock-output-names = "dpll_dsp_m2_ck";
401 assigned-clock-rates = <600000000>;
404 iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
405 #clock-cells = <0>;
406 compatible = "fixed-factor-clock";
407 clock-output-names = "iva_dpll_hs_clk_div";
409 clock-mult = <1>;
410 clock-div = <1>;
413 dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
414 #clock-cells = <0>;
415 compatible = "ti,mux-clock";
416 clock-output-names = "dpll_iva_byp_mux";
422 dpll_iva_ck: clock@1a0 {
423 #clock-cells = <0>;
424 compatible = "ti,omap4-dpll-clock";
425 clock-output-names = "dpll_iva_ck";
429 assigned-clock-rates = <1165000000>;
432 dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
433 #clock-cells = <0>;
434 compatible = "ti,divider-clock";
435 clock-output-names = "dpll_iva_m2_ck";
443 assigned-clock-rates = <388333334>;
446 iva_dclk: clock-iva-dclk {
447 #clock-cells = <0>;
448 compatible = "fixed-factor-clock";
449 clock-output-names = "iva_dclk";
451 clock-mult = <1>;
452 clock-div = <1>;
455 dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
456 #clock-cells = <0>;
457 compatible = "ti,mux-clock";
458 clock-output-names = "dpll_gpu_byp_mux";
464 dpll_gpu_ck: clock@2d8 {
465 #clock-cells = <0>;
466 compatible = "ti,omap4-dpll-clock";
467 clock-output-names = "dpll_gpu_ck";
471 assigned-clock-rates = <1277000000>;
474 dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
475 #clock-cells = <0>;
476 compatible = "ti,divider-clock";
477 clock-output-names = "dpll_gpu_m2_ck";
485 assigned-clock-rates = <425666667>;
488 dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
489 #clock-cells = <0>;
490 compatible = "ti,divider-clock";
491 clock-output-names = "dpll_core_m2_ck";
500 core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
501 #clock-cells = <0>;
502 compatible = "fixed-factor-clock";
503 clock-output-names = "core_dpll_out_dclk_div";
505 clock-mult = <1>;
506 clock-div = <1>;
509 dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
510 #clock-cells = <0>;
511 compatible = "ti,mux-clock";
512 clock-output-names = "dpll_ddr_byp_mux";
518 dpll_ddr_ck: clock@210 {
519 #clock-cells = <0>;
520 compatible = "ti,omap4-dpll-clock";
521 clock-output-names = "dpll_ddr_ck";
526 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
527 #clock-cells = <0>;
528 compatible = "ti,divider-clock";
529 clock-output-names = "dpll_ddr_m2_ck";
538 dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
539 #clock-cells = <0>;
540 compatible = "ti,mux-clock";
541 clock-output-names = "dpll_gmac_byp_mux";
547 dpll_gmac_ck: clock@2a8 {
548 #clock-cells = <0>;
549 compatible = "ti,omap4-dpll-clock";
550 clock-output-names = "dpll_gmac_ck";
555 dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
556 #clock-cells = <0>;
557 compatible = "ti,divider-clock";
558 clock-output-names = "dpll_gmac_m2_ck";
567 video2_dclk_div: clock-video2-dclk-div {
568 #clock-cells = <0>;
569 compatible = "fixed-factor-clock";
570 clock-output-names = "video2_dclk_div";
572 clock-mult = <1>;
573 clock-div = <1>;
576 video1_dclk_div: clock-video1-dclk-div {
577 #clock-cells = <0>;
578 compatible = "fixed-factor-clock";
579 clock-output-names = "video1_dclk_div";
581 clock-mult = <1>;
582 clock-div = <1>;
585 hdmi_dclk_div: clock-hdmi-dclk-div {
586 #clock-cells = <0>;
587 compatible = "fixed-factor-clock";
588 clock-output-names = "hdmi_dclk_div";
590 clock-mult = <1>;
591 clock-div = <1>;
594 per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
595 #clock-cells = <0>;
596 compatible = "fixed-factor-clock";
597 clock-output-names = "per_dpll_hs_clk_div";
599 clock-mult = <1>;
600 clock-div = <2>;
603 usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
604 #clock-cells = <0>;
605 compatible = "fixed-factor-clock";
606 clock-output-names = "usb_dpll_hs_clk_div";
608 clock-mult = <1>;
609 clock-div = <3>;
612 eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
613 #clock-cells = <0>;
614 compatible = "fixed-factor-clock";
615 clock-output-names = "eve_dpll_hs_clk_div";
617 clock-mult = <1>;
618 clock-div = <1>;
621 dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
622 #clock-cells = <0>;
623 compatible = "ti,mux-clock";
624 clock-output-names = "dpll_eve_byp_mux";
630 dpll_eve_ck: clock@284 {
631 #clock-cells = <0>;
632 compatible = "ti,omap4-dpll-clock";
633 clock-output-names = "dpll_eve_ck";
638 dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
639 #clock-cells = <0>;
640 compatible = "ti,divider-clock";
641 clock-output-names = "dpll_eve_m2_ck";
650 eve_dclk_div: clock-eve-dclk-div {
651 #clock-cells = <0>;
652 compatible = "fixed-factor-clock";
653 clock-output-names = "eve_dclk_div";
655 clock-mult = <1>;
656 clock-div = <1>;
659 dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
660 #clock-cells = <0>;
661 compatible = "ti,divider-clock";
662 clock-output-names = "dpll_core_h13x2_ck";
671 dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
672 #clock-cells = <0>;
673 compatible = "ti,divider-clock";
674 clock-output-names = "dpll_core_h14x2_ck";
683 dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
684 #clock-cells = <0>;
685 compatible = "ti,divider-clock";
686 clock-output-names = "dpll_core_h22x2_ck";
695 dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
696 #clock-cells = <0>;
697 compatible = "ti,divider-clock";
698 clock-output-names = "dpll_core_h23x2_ck";
707 dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
708 #clock-cells = <0>;
709 compatible = "ti,divider-clock";
710 clock-output-names = "dpll_core_h24x2_ck";
719 dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
720 #clock-cells = <0>;
721 compatible = "ti,omap4-dpll-x2-clock";
722 clock-output-names = "dpll_ddr_x2_ck";
726 dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
727 #clock-cells = <0>;
728 compatible = "ti,divider-clock";
729 clock-output-names = "dpll_ddr_h11x2_ck";
738 dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
739 #clock-cells = <0>;
740 compatible = "ti,omap4-dpll-x2-clock";
741 clock-output-names = "dpll_dsp_x2_ck";
745 dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
746 #clock-cells = <0>;
747 compatible = "ti,divider-clock";
748 clock-output-names = "dpll_dsp_m3x2_ck";
756 assigned-clock-rates = <400000000>;
759 dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
760 #clock-cells = <0>;
761 compatible = "ti,omap4-dpll-x2-clock";
762 clock-output-names = "dpll_gmac_x2_ck";
766 dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
767 #clock-cells = <0>;
768 compatible = "ti,divider-clock";
769 clock-output-names = "dpll_gmac_h11x2_ck";
778 dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
779 #clock-cells = <0>;
780 compatible = "ti,divider-clock";
781 clock-output-names = "dpll_gmac_h12x2_ck";
790 dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
791 #clock-cells = <0>;
792 compatible = "ti,divider-clock";
793 clock-output-names = "dpll_gmac_h13x2_ck";
802 dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
803 #clock-cells = <0>;
804 compatible = "ti,divider-clock";
805 clock-output-names = "dpll_gmac_m3x2_ck";
814 gmii_m_clk_div: clock-gmii-m-clk-div {
815 #clock-cells = <0>;
816 compatible = "fixed-factor-clock";
817 clock-output-names = "gmii_m_clk_div";
819 clock-mult = <1>;
820 clock-div = <2>;
823 hdmi_clk2_div: clock-hdmi-clk2-div {
824 #clock-cells = <0>;
825 compatible = "fixed-factor-clock";
826 clock-output-names = "hdmi_clk2_div";
828 clock-mult = <1>;
829 clock-div = <1>;
832 hdmi_div_clk: clock-hdmi-div {
833 #clock-cells = <0>;
834 compatible = "fixed-factor-clock";
835 clock-output-names = "hdmi_div_clk";
837 clock-mult = <1>;
838 clock-div = <1>;
841 l3_iclk_div: clock-l3-iclk-div-4@100 {
842 #clock-cells = <0>;
843 compatible = "ti,divider-clock";
844 clock-output-names = "l3_iclk_div";
852 l4_root_clk_div: clock-l4-root-clk-div {
853 #clock-cells = <0>;
854 compatible = "fixed-factor-clock";
855 clock-output-names = "l4_root_clk_div";
857 clock-mult = <1>;
858 clock-div = <2>;
861 video1_clk2_div: clock-video1-clk2-div {
862 #clock-cells = <0>;
863 compatible = "fixed-factor-clock";
864 clock-output-names = "video1_clk2_div";
866 clock-mult = <1>;
867 clock-div = <1>;
870 video1_div_clk: clock-video1-div {
871 #clock-cells = <0>;
872 compatible = "fixed-factor-clock";
873 clock-output-names = "video1_div_clk";
875 clock-mult = <1>;
876 clock-div = <1>;
879 video2_clk2_div: clock-video2-clk2-div {
880 #clock-cells = <0>;
881 compatible = "fixed-factor-clock";
882 clock-output-names = "video2_clk2_div";
884 clock-mult = <1>;
885 clock-div = <1>;
888 video2_div_clk: clock-video2-div {
889 #clock-cells = <0>;
890 compatible = "fixed-factor-clock";
891 clock-output-names = "video2_div_clk";
893 clock-mult = <1>;
894 clock-div = <1>;
897 dummy_ck: clock-dummy {
898 #clock-cells = <0>;
899 compatible = "fixed-clock";
900 clock-output-names = "dummy_ck";
901 clock-frequency = <0>;
905 sys_clkin1: clock-sys-clkin1@110 {
906 #clock-cells = <0>;
907 compatible = "ti,mux-clock";
908 clock-output-names = "sys_clkin1";
914 abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
915 #clock-cells = <0>;
916 compatible = "ti,mux-clock";
917 clock-output-names = "abe_dpll_sys_clk_mux";
922 abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
923 #clock-cells = <0>;
924 compatible = "ti,mux-clock";
925 clock-output-names = "abe_dpll_bypass_clk_mux";
930 abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
931 #clock-cells = <0>;
932 compatible = "ti,mux-clock";
933 clock-output-names = "abe_dpll_clk_mux";
938 abe_24m_fclk: clock-abe-24m@11c {
939 #clock-cells = <0>;
940 compatible = "ti,divider-clock";
941 clock-output-names = "abe_24m_fclk";
947 aess_fclk: clock-aess@178 {
948 #clock-cells = <0>;
949 compatible = "ti,divider-clock";
950 clock-output-names = "aess_fclk";
956 abe_giclk_div: clock-abe-giclk-div@174 {
957 #clock-cells = <0>;
958 compatible = "ti,divider-clock";
959 clock-output-names = "abe_giclk_div";
965 abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
966 #clock-cells = <0>;
967 compatible = "ti,divider-clock";
968 clock-output-names = "abe_lp_clk_div";
974 abe_sys_clk_div: clock-abe-sys-clk-div@120 {
975 #clock-cells = <0>;
976 compatible = "ti,divider-clock";
977 clock-output-names = "abe_sys_clk_div";
983 adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
984 #clock-cells = <0>;
985 compatible = "ti,mux-clock";
986 clock-output-names = "adc_gfclk_mux";
991 sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
992 #clock-cells = <0>;
993 compatible = "ti,divider-clock";
994 clock-output-names = "sys_clk1_dclk_div";
1001 sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
1002 #clock-cells = <0>;
1003 compatible = "ti,divider-clock";
1004 clock-output-names = "sys_clk2_dclk_div";
1011 per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
1012 #clock-cells = <0>;
1013 compatible = "ti,divider-clock";
1014 clock-output-names = "per_abe_x1_dclk_div";
1021 dsp_gclk_div: clock-dsp-gclk-div@18c {
1022 #clock-cells = <0>;
1023 compatible = "ti,divider-clock";
1024 clock-output-names = "dsp_gclk_div";
1031 gpu_dclk: clock-gpu-dclk@1a0 {
1032 #clock-cells = <0>;
1033 compatible = "ti,divider-clock";
1034 clock-output-names = "gpu_dclk";
1041 emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
1042 #clock-cells = <0>;
1043 compatible = "ti,divider-clock";
1044 clock-output-names = "emif_phy_dclk_div";
1051 gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
1052 #clock-cells = <0>;
1053 compatible = "ti,divider-clock";
1054 clock-output-names = "gmac_250m_dclk_div";
1061 gmac_main_clk: clock-gmac-main {
1062 #clock-cells = <0>;
1063 compatible = "fixed-factor-clock";
1064 clock-output-names = "gmac_main_clk";
1066 clock-mult = <1>;
1067 clock-div = <2>;
1070 l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
1071 #clock-cells = <0>;
1072 compatible = "ti,divider-clock";
1073 clock-output-names = "l3init_480m_dclk_div";
1080 usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
1081 #clock-cells = <0>;
1082 compatible = "ti,divider-clock";
1083 clock-output-names = "usb_otg_dclk_div";
1090 sata_dclk_div: clock-sata-dclk-div@1c0 {
1091 #clock-cells = <0>;
1092 compatible = "ti,divider-clock";
1093 clock-output-names = "sata_dclk_div";
1100 pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
1101 #clock-cells = <0>;
1102 compatible = "ti,divider-clock";
1103 clock-output-names = "pcie2_dclk_div";
1110 pcie_dclk_div: clock-pcie-dclk-div@1b4 {
1111 #clock-cells = <0>;
1112 compatible = "ti,divider-clock";
1113 clock-output-names = "pcie_dclk_div";
1120 emu_dclk_div: clock-emu-dclk-div@194 {
1121 #clock-cells = <0>;
1122 compatible = "ti,divider-clock";
1123 clock-output-names = "emu_dclk_div";
1130 secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
1131 #clock-cells = <0>;
1132 compatible = "ti,divider-clock";
1133 clock-output-names = "secure_32k_dclk_div";
1140 clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
1141 #clock-cells = <0>;
1142 compatible = "ti,mux-clock";
1143 clock-output-names = "clkoutmux0_clk_mux";
1148 clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
1149 #clock-cells = <0>;
1150 compatible = "ti,mux-clock";
1151 clock-output-names = "clkoutmux1_clk_mux";
1156 clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
1157 #clock-cells = <0>;
1158 compatible = "ti,mux-clock";
1159 clock-output-names = "clkoutmux2_clk_mux";
1164 custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
1165 #clock-cells = <0>;
1166 compatible = "fixed-factor-clock";
1167 clock-output-names = "custefuse_sys_gfclk_div";
1169 clock-mult = <1>;
1170 clock-div = <2>;
1173 eve_clk: clock-eve@180 {
1174 #clock-cells = <0>;
1175 compatible = "ti,mux-clock";
1176 clock-output-names = "eve_clk";
1181 hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
1182 #clock-cells = <0>;
1183 compatible = "ti,mux-clock";
1184 clock-output-names = "hdmi_dpll_clk_mux";
1189 mlb_clk: clock-mlb@134 {
1190 #clock-cells = <0>;
1191 compatible = "ti,divider-clock";
1192 clock-output-names = "mlb_clk";
1199 mlbp_clk: clock-mlbp@130 {
1200 #clock-cells = <0>;
1201 compatible = "ti,divider-clock";
1202 clock-output-names = "mlbp_clk";
1209 per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
1210 #clock-cells = <0>;
1211 compatible = "ti,divider-clock";
1212 clock-output-names = "per_abe_x1_gfclk2_div";
1219 timer_sys_clk_div: clock-timer-sys-clk-div@144 {
1220 #clock-cells = <0>;
1221 compatible = "ti,divider-clock";
1222 clock-output-names = "timer_sys_clk_div";
1228 video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
1229 #clock-cells = <0>;
1230 compatible = "ti,mux-clock";
1231 clock-output-names = "video1_dpll_clk_mux";
1236 video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
1237 #clock-cells = <0>;
1238 compatible = "ti,mux-clock";
1239 clock-output-names = "video2_dpll_clk_mux";
1244 wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
1245 #clock-cells = <0>;
1246 compatible = "ti,mux-clock";
1247 clock-output-names = "wkupaon_iclk_mux";
1254 dpll_pcie_ref_ck: clock@200 {
1255 #clock-cells = <0>;
1256 compatible = "ti,omap4-dpll-clock";
1257 clock-output-names = "dpll_pcie_ref_ck";
1262 dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
1263 #clock-cells = <0>;
1264 compatible = "ti,divider-clock";
1265 clock-output-names = "dpll_pcie_ref_m2ldo_ck";
1274 apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
1275 compatible = "ti,mux-clock";
1276 clock-output-names = "apll_pcie_in_clk_mux";
1278 #clock-cells = <0>;
1283 apll_pcie_ck: clock@21c {
1284 #clock-cells = <0>;
1285 compatible = "ti,dra7-apll-clock";
1286 clock-output-names = "apll_pcie_ck";
1291 optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
1292 compatible = "ti,divider-clock";
1293 clock-output-names = "optfclk_pciephy_div";
1295 #clock-cells = <0>;
1302 apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
1303 #clock-cells = <0>;
1304 compatible = "fixed-factor-clock";
1305 clock-output-names = "apll_pcie_clkvcoldo";
1307 clock-mult = <1>;
1308 clock-div = <1>;
1311 apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
1312 #clock-cells = <0>;
1313 compatible = "fixed-factor-clock";
1314 clock-output-names = "apll_pcie_clkvcoldo_div";
1316 clock-mult = <1>;
1317 clock-div = <1>;
1320 apll_pcie_m2_ck: clock-apll-pcie-m2 {
1321 #clock-cells = <0>;
1322 compatible = "fixed-factor-clock";
1323 clock-output-names = "apll_pcie_m2_ck";
1325 clock-mult = <1>;
1326 clock-div = <1>;
1329 dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
1330 #clock-cells = <0>;
1331 compatible = "ti,mux-clock";
1332 clock-output-names = "dpll_per_byp_mux";
1338 dpll_per_ck: clock@140 {
1339 #clock-cells = <0>;
1340 compatible = "ti,omap4-dpll-clock";
1341 clock-output-names = "dpll_per_ck";
1346 dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
1347 #clock-cells = <0>;
1348 compatible = "ti,divider-clock";
1349 clock-output-names = "dpll_per_m2_ck";
1358 func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
1359 #clock-cells = <0>;
1360 compatible = "fixed-factor-clock";
1361 clock-output-names = "func_96m_aon_dclk_div";
1363 clock-mult = <1>;
1364 clock-div = <1>;
1367 dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
1368 #clock-cells = <0>;
1369 compatible = "ti,mux-clock";
1370 clock-output-names = "dpll_usb_byp_mux";
1376 dpll_usb_ck: clock@180 {
1377 #clock-cells = <0>;
1378 compatible = "ti,omap4-dpll-j-type-clock";
1379 clock-output-names = "dpll_usb_ck";
1384 dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
1385 #clock-cells = <0>;
1386 compatible = "ti,divider-clock";
1387 clock-output-names = "dpll_usb_m2_ck";
1396 dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
1397 #clock-cells = <0>;
1398 compatible = "ti,divider-clock";
1399 clock-output-names = "dpll_pcie_ref_m2_ck";
1408 dpll_per_x2_ck: clock-dpll-per-x2 {
1409 #clock-cells = <0>;
1410 compatible = "ti,omap4-dpll-x2-clock";
1411 clock-output-names = "dpll_per_x2_ck";
1415 dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
1416 #clock-cells = <0>;
1417 compatible = "ti,divider-clock";
1418 clock-output-names = "dpll_per_h11x2_ck";
1427 dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
1428 #clock-cells = <0>;
1429 compatible = "ti,divider-clock";
1430 clock-output-names = "dpll_per_h12x2_ck";
1439 dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
1440 #clock-cells = <0>;
1441 compatible = "ti,divider-clock";
1442 clock-output-names = "dpll_per_h13x2_ck";
1451 dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
1452 #clock-cells = <0>;
1453 compatible = "ti,divider-clock";
1454 clock-output-names = "dpll_per_h14x2_ck";
1463 dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
1464 #clock-cells = <0>;
1465 compatible = "ti,divider-clock";
1466 clock-output-names = "dpll_per_m2x2_ck";
1475 dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
1476 #clock-cells = <0>;
1477 compatible = "fixed-factor-clock";
1478 clock-output-names = "dpll_usb_clkdcoldo";
1480 clock-mult = <1>;
1481 clock-div = <1>;
1484 func_128m_clk: clock-func-128m {
1485 #clock-cells = <0>;
1486 compatible = "fixed-factor-clock";
1487 clock-output-names = "func_128m_clk";
1489 clock-mult = <1>;
1490 clock-div = <2>;
1493 func_12m_fclk: clock-func-12m-fclk {
1494 #clock-cells = <0>;
1495 compatible = "fixed-factor-clock";
1496 clock-output-names = "func_12m_fclk";
1498 clock-mult = <1>;
1499 clock-div = <16>;
1502 func_24m_clk: clock-func-24m {
1503 #clock-cells = <0>;
1504 compatible = "fixed-factor-clock";
1505 clock-output-names = "func_24m_clk";
1507 clock-mult = <1>;
1508 clock-div = <4>;
1511 func_48m_fclk: clock-func-48m-fclk {
1512 #clock-cells = <0>;
1513 compatible = "fixed-factor-clock";
1514 clock-output-names = "func_48m_fclk";
1516 clock-mult = <1>;
1517 clock-div = <4>;
1520 func_96m_fclk: clock-func-96m-fclk {
1521 #clock-cells = <0>;
1522 compatible = "fixed-factor-clock";
1523 clock-output-names = "func_96m_fclk";
1525 clock-mult = <1>;
1526 clock-div = <2>;
1529 l3init_60m_fclk: clock-l3init-60m@104 {
1530 #clock-cells = <0>;
1531 compatible = "ti,divider-clock";
1532 clock-output-names = "l3init_60m_fclk";
1538 clkout2_clk: clock-clkout2-8@6b0 {
1539 #clock-cells = <0>;
1540 compatible = "ti,gate-clock";
1541 clock-output-names = "clkout2_clk";
1547 l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
1548 #clock-cells = <0>;
1549 compatible = "ti,gate-clock";
1550 clock-output-names = "l3init_960m_gfclk";
1556 usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
1557 #clock-cells = <0>;
1558 compatible = "ti,gate-clock";
1559 clock-output-names = "usb_phy1_always_on_clk32k";
1565 usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
1566 #clock-cells = <0>;
1567 compatible = "ti,gate-clock";
1568 clock-output-names = "usb_phy2_always_on_clk32k";
1574 usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
1575 #clock-cells = <0>;
1576 compatible = "ti,gate-clock";
1577 clock-output-names = "usb_phy3_always_on_clk32k";
1583 gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
1584 #clock-cells = <0>;
1585 compatible = "ti,mux-clock";
1586 clock-output-names = "gpu_core_gclk_mux";
1591 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1594 gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
1595 #clock-cells = <0>;
1596 compatible = "ti,mux-clock";
1597 clock-output-names = "gpu_hyd_gclk_mux";
1602 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1605 l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
1606 #clock-cells = <0>;
1607 compatible = "ti,divider-clock";
1608 clock-output-names = "l3instr_ts_gclk_div";
1615 vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
1616 #clock-cells = <0>;
1617 compatible = "ti,mux-clock";
1618 clock-output-names = "vip1_gclk_mux";
1624 vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
1625 #clock-cells = <0>;
1626 compatible = "ti,mux-clock";
1627 clock-output-names = "vip2_gclk_mux";
1633 vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 {
1634 #clock-cells = <0>;
1635 compatible = "ti,mux-clock";
1636 clock-output-names = "vip3_gclk_mux";
1644 coreaon_clkdm: clock-coreaon-clkdm {
1646 clock-output-names = "coreaon_clkdm";
1652 dss_deshdcp_clk: clock-dss-deshdcp-0@558 {
1653 #clock-cells = <0>;
1654 compatible = "ti,gate-clock";
1655 clock-output-names = "dss_deshdcp_clk";
1661 ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 {
1662 #clock-cells = <0>;
1663 compatible = "ti,gate-clock";
1664 clock-output-names = "ehrpwm0_tbclk";
1670 ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 {
1671 #clock-cells = <0>;
1672 compatible = "ti,gate-clock";
1673 clock-output-names = "ehrpwm1_tbclk";
1679 ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 {
1680 #clock-cells = <0>;
1681 compatible = "ti,gate-clock";
1682 clock-output-names = "ehrpwm2_tbclk";
1688 sys_32k_ck: clock-sys-32k {
1689 #clock-cells = <0>;
1690 compatible = "ti,mux-clock";
1691 clock-output-names = "sys_32k_ck";
1699 mpu_cm: clock@300 {
1701 clock-output-names = "mpu_cm";
1707 mpu_clkctrl: clock@20 {
1709 clock-output-names = "mpu_clkctrl";
1711 #clock-cells = <2>;
1716 dsp1_cm: clock@400 {
1718 clock-output-names = "dsp1_cm";
1724 dsp1_clkctrl: clock@20 {
1726 clock-output-names = "dsp1_clkctrl";
1728 #clock-cells = <2>;
1733 ipu_cm: clock@500 {
1735 clock-output-names = "ipu_cm";
1741 ipu1_clkctrl: clock@20 {
1743 clock-output-names = "ipu1_clkctrl";
1745 #clock-cells = <2>;
1747 assigned-clock-parents = <&dpll_core_h22x2_ck>;
1750 ipu_clkctrl: clock@50 {
1752 clock-output-names = "ipu_clkctrl";
1754 #clock-cells = <2>;
1759 dsp2_cm: clock@600 {
1761 clock-output-names = "dsp2_cm";
1767 dsp2_clkctrl: clock@20 {
1769 clock-output-names = "dsp2_clkctrl";
1771 #clock-cells = <2>;
1776 rtc_cm: clock@700 {
1778 clock-output-names = "rtc_cm";
1784 rtc_clkctrl: clock@20 {
1786 clock-output-names = "rtc_clkctrl";
1788 #clock-cells = <2>;
1792 vpe_cm: clock@760 {
1794 clock-output-names = "vpe_cm";
1800 vpe_clkctrl: clock@0 {
1802 clock-output-names = "vpe_clkctrl";
1804 #clock-cells = <2>;
1811 coreaon_cm: clock@600 {
1813 clock-output-names = "coreaon_cm";
1819 coreaon_clkctrl: clock@20 {
1821 clock-output-names = "coreaon_clkctrl";
1823 #clock-cells = <2>;
1827 l3main1_cm: clock@700 {
1829 clock-output-names = "l3main1_cm";
1835 l3main1_clkctrl: clock@20 {
1837 clock-output-names = "l3main1_clkctrl";
1839 #clock-cells = <2>;
1844 ipu2_cm: clock@900 {
1846 clock-output-names = "ipu2_cm";
1852 ipu2_clkctrl: clock@20 {
1854 clock-output-names = "ipu2_clkctrl";
1856 #clock-cells = <2>;
1861 dma_cm: clock@a00 {
1863 clock-output-names = "dma_cm";
1869 dma_clkctrl: clock@20 {
1871 clock-output-names = "dma_clkctrl";
1873 #clock-cells = <2>;
1877 emif_cm: clock@b00 {
1879 clock-output-names = "emif_cm";
1885 emif_clkctrl: clock@20 {
1887 clock-output-names = "emif_clkctrl";
1889 #clock-cells = <2>;
1893 atl_cm: clock@c00 {
1895 clock-output-names = "atl_cm";
1901 atl_clkctrl: clock@0 {
1903 clock-output-names = "atl_clkctrl";
1905 #clock-cells = <2>;
1909 l4cfg_cm: clock@d00 {
1911 clock-output-names = "l4cfg_cm";
1917 l4cfg_clkctrl: clock@20 {
1919 clock-output-names = "l4cfg_clkctrl";
1921 #clock-cells = <2>;
1925 l3instr_cm: clock@e00 {
1927 clock-output-names = "l3instr_cm";
1933 l3instr_clkctrl: clock@20 {
1935 clock-output-names = "l3instr_clkctrl";
1937 #clock-cells = <2>;
1941 iva_cm: clock@f00 {
1943 clock-output-names = "iva_cm";
1949 iva_clkctrl: clock@20 {
1951 clock-output-names = "iva_clkctrl";
1953 #clock-cells = <2>;
1957 cam_cm: clock@1000 {
1959 clock-output-names = "cam_cm";
1965 cam_clkctrl: clock@20 {
1967 clock-output-names = "cam_clkctrl";
1969 #clock-cells = <2>;
1973 dss_cm: clock@1100 {
1975 clock-output-names = "dss_cm";
1981 dss_clkctrl: clock@20 {
1983 clock-output-names = "dss_clkctrl";
1985 #clock-cells = <2>;
1989 gpu_cm: clock@1200 {
1991 clock-output-names = "gpu_cm";
1997 gpu_clkctrl: clock@20 {
1999 clock-output-names = "gpu_clkctrl";
2001 #clock-cells = <2>;
2005 l3init_cm: clock@1300 {
2007 clock-output-names = "l3init_cm";
2013 l3init_clkctrl: clock@20 {
2015 clock-output-names = "l3init_clkctrl";
2017 #clock-cells = <2>;
2020 pcie_clkctrl: clock@b0 {
2022 clock-output-names = "pcie_clkctrl";
2024 #clock-cells = <2>;
2027 gmac_clkctrl: clock@d0 {
2029 clock-output-names = "gmac_clkctrl";
2031 #clock-cells = <2>;
2036 l4per_cm: clock@1700 {
2038 clock-output-names = "l4per_cm";
2044 l4per_clkctrl: clock@28 {
2046 clock-output-names = "l4per_clkctrl";
2048 #clock-cells = <2>;
2051 assigned-clock-parents = <&abe_24m_fclk>;
2054 l4sec_clkctrl: clock@1a0 {
2056 clock-output-names = "l4sec_clkctrl";
2058 #clock-cells = <2>;
2061 l4per2_clkctrl: clock@c {
2063 clock-output-names = "l4per2_clkctrl";
2065 #clock-cells = <2>;
2068 l4per3_clkctrl: clock@14 {
2070 clock-output-names = "l4per3_clkctrl";
2072 #clock-cells = <2>;
2079 wkupaon_cm: clock@1800 {
2081 clock-output-names = "wkupaon_cm";
2087 wkupaon_clkctrl: clock@20 {
2089 clock-output-names = "wkupaon_clkctrl";
2091 #clock-cells = <2>;