Lines Matching refs:posted

76 are burned by the fact that PCI bus writes are posted asynchronously. A
176   Note that posted writes are not strictly ordered against a spinlock, see
252   number. PCI requires I/O port access to be non-posted, meaning that an outb()
256   implementations and CPU architectures however fail to implement non-posted I/O
257   space on PCI, so they can end up being posted on such hardware.
324 mappings are posted, which means that the CPU does not wait for the write to
373 Like ioremap(), but explicitly requests non-posted write semantics. On some
374 architectures and buses, ioremap() mappings have posted write semantics, which
378 due to the posted write semantics, this is not the case with respect to other
379 devices. ioremap_np() explicitly requests non-posted semantics, which means
392 platform-specific or they derive benefit from non-posted writes where
394 ensure posted write completion is to do a dummy read after a write as
399 always posted, even on architectures that otherwise implement ioremap_np().
400 Using ioremap_np() for PCI BARs will at best result in posted write semantics,
403 Note that non-posted write semantics are orthogonal to CPU-side ordering
405 non-posted write instruction retires. See the previous section on MMIO access
476   require non-posted writes for certain buses (see the nonposted-mmio and
477   posted-mmio device tree properties).