Lines Matching refs:description

12 description:
23       - description: MSS QDSP6 registers
24       - description: RMB registers
33       - description: MSA Stream 1
34       - description: MSA Stream 2
38       - description: Watchdog interrupt
39       - description: Fatal interrupt
40       - description: Ready interrupt
41       - description: Handover interrupt
42       - description: Stop acknowledge interrupt
43       - description: Shutdown acknowledge interrupt
56       - description: GCC MSS IFACE clock
57       - description: GCC MSS BUS clock
58       - description: GCC MSS NAV clock
59       - description: GCC MSS SNOC_AXI clock
60       - description: GCC MSS MFAB_AXIS clock
61       - description: RPMH XO clock
74       - description: CX power domain
75       - description: MX power domain
76       - description: MSS power domain
86       - description: AOSS restart
87       - description: PDC reset
96       - description: MBA reserved region
97       - description: modem reserved region
98       - description: metadata reserved region
103       - description: Name of MBA firmware
104       - description: Name of modem firmware
108     description:
113           - description: phandle to TCSR_MUTEX registers
114           - description: offset to the Q6 halt register
115           - description: offset to the modem halt register
116           - description: offset to the nc halt register
120     description:
125           - description: phandle to TCSR_MUTEX registers
126           - description: offset to the conn_box_spare0 register
130     description: Reference to the AOSS side-channel message RAM.
134     description: States used by the AP to signal the Hexagon core
136       - description: Stop the modem
139     description: The names of the state bits used for SMP2P output
145     description:
152           - description: IRQ from MSS to GLINK
156           - description: Mailbox for communication between APPS and MSS