Lines Matching refs:cycles

15   byte 0 TCLR  : CLE to RE delay in number of AHB clock cycles, only 4 bits
17                  cycles.
19   byte 2 THIZ  : number of HCLK clock cycles during which the data bus is
21                  Only valid for write transactions. Zero means zero cycles,
22                  255 means 255 cycles.
23   byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
25                  one cycle, 255 means 256 cycles.
26   byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
28                  255 means 256 cycles.
29   byte 5 TSET  : number of HCLK clock cycles to assert the address before the
31                  cycles.