Lines Matching refs:cycles

46       of clock cycles.
53       SELF REFRESH) in terms of number of clock cycles.
60       cycles.
66       Four-bank activate window in terms of number of clock cycles.
72       Mode register set command delay in terms of number of clock cycles.
79       of clock cycles.
85       Row active time in terms of number of clock cycles.
91       ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
97       RAS-to-CAS delay in terms of number of clock cycles.
103       Refresh Cycle time in terms of number of clock cycles.
109      READ data latency in terms of number of clock cycles.
115       Row precharge time (all banks) in terms of number of clock cycles.
121       Row precharge time (single banks) in terms of number of clock cycles.
127       Active bank A to active bank B in terms of number of clock cycles.
134       cycles.
141       of clock cycles.
147       WRITE data latency in terms of number of clock cycles.
153       WRITE recovery time in terms of number of clock cycles.
159       Internal WRITE-to-READ command delay in terms of number of clock cycles.
166       cycles.
173       cycles.