Lines Matching refs:cycles

53       Active bank a to active bank b in terms of number of clock cycles.
60       Internal WRITE-to-READ command delay in terms of number of clock cycles.
68       cycles. Obtained from device datasheet.
75       cycles. Obtained from device datasheet.
82       of clock cycles. Obtained from device datasheet.
88       Row precharge time (all banks) in terms of number of clock cycles.
95       RAS-to-CAS delay in terms of number of clock cycles. Obtained from
102       WRITE recovery time in terms of number of clock cycles. Obtained from
109       Row active time in terms of number of clock cycles. Obtained from device
117       SELF REFRESH) in terms of number of clock cycles. Obtained from device
124       Four-bank activate window in terms of number of clock cycles. Obtained