Lines Matching refs:trap
103 the corresponding cacheline, a memory corruption trap occurs. By
104 default, it is a disrupting trap and is sent to the hypervisor
106 resumable error (TT=0x7e) trap to the kernel. The kernel sends
107 a SIGSEGV to the task that resulted in this trap with the following
123 the corresponding cacheline, a memory corruption trap occurs. If
126 a SIGSEGV to the task that resulted in this trap with the following
132 siginfo.si_addr = addr; /* address that caused trap */
136 ADI tag mismatch on a load always results in precise trap.
143 on a memory address, processor sends an MCD disabled trap. This
144 trap is handled by hypervisor first and the hypervisor vectors this
145 trap through to the kernel as Data Access Exception trap with
152 siginfo.si_addr = addr; /* address that caused trap */