Lines Matching refs:be
20 hypervisor code, or it may just be a handful of instructions for
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
51 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
52 using blocks of up to 2 megabytes in size, it must not be placed within
53 any 2M region which must be mapped with any specific attributes.
55 NOTE: versions prior to v4.2 also require that the DTB be placed within
64 therefore requires decompression (gzip etc.) to be performed by the boot
103 little-endian and must be respected. Where image_size is zero,
104 text_offset can be assumed to be 0x80000.
120 2MB aligned base should be as close as possible
135 The Image must be placed text_offset bytes from a 2MB aligned base
138 special significance to the kernel, and may be used for other purposes.
139 At least image_size bytes from the start of the image must be free for
142 physical offset of the Image so it is recommended that the Image be
151 memreserve region in the device tree) will be considered as available to
154 Before jumping into the kernel, the following conditions must be met:
169 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
171 The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
176 The MMU must be off.
178 The instruction cache may be on or off, and must not hold any stale
181 The address range corresponding to the loaded kernel image must be
186 operations must be configured and may be enabled.
188 operations (not recommended) must be configured and disabled.
192 CNTFRQ must be programmed with the timer frequency and CNTVOFF must
193 be programmed with a consistent value on all CPUs. If entering the
199 All CPUs to be booted by the kernel must be part of the same coherency
207 level where the kernel image will be entered must be initialised by
216 - The value of SCR_EL3.FIQ must be the same as the one present at boot
221 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
223 For systems with a GICv3 interrupt controller to be used in v3 mode:
226 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
227 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
228 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
234 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
235 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
239 For systems with a GICv3 interrupt controller to be used in
244 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
248 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
256 - SCR_EL3.APK (bit 16) must be initialised to 0b1
257 - SCR_EL3.API (bit 17) must be initialised to 0b1
261 - HCR_EL2.APK (bit 40) must be initialised to 0b1
262 - HCR_EL2.API (bit 41) must be initialised to 0b1
268 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
269 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
270 - AMCNTENSET0_EL0 must be initialised to 0b1111
271 - AMCNTENSET1_EL0 must be initialised to a platform specific value
277 - AMCNTENSET0_EL0 must be initialised to 0b1111
278 - AMCNTENSET1_EL0 must be initialised to a platform specific value
286 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
292 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
298 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
302 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
308 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
310 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
315 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
317 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
319 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
326 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
328 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
330 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
335 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
337 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
339 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
341 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
344 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
346 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
348 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
350 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
356 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
360 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
366 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
370 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
376 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
380 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
386 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
392 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
396 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
402 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
406 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
408 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
410 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
412 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
417 disable traps it is permissible for these traps to be enabled so long as
438 device tree) polling their cpu-release-addr location, which must be
439 contained in the reserved region. A wfe instruction may be inserted
440 to reduce the overhead of the busy-loop and a sev will be issued by
443 value. The value will be written as a single 64-bit little-endian