119 	u32 temp_reg = 0;  in set_prot_desc_tx()  local
121 	temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode);  in set_prot_desc_tx()
122 	temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode);  in set_prot_desc_tx()
123 	temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1);  in set_prot_desc_tx()
124 	temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2);  in set_prot_desc_tx()
126 		temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1);  in set_prot_desc_tx()
127 		temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2);  in set_prot_desc_tx()
129 		temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);  in set_prot_desc_tx()
130 		temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);  in set_prot_desc_tx()
132 	temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay);  in set_prot_desc_tx()
133 	temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order);  in set_prot_desc_tx()
134 	temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol);  in set_prot_desc_tx()
135 	temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap);  in set_prot_desc_tx()
136 	temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode);  in set_prot_desc_tx()
137 	temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);  in set_prot_desc_tx()
139 	writel(temp_reg, msp->registers + MSP_TCF);  in set_prot_desc_tx()
146 	u32 temp_reg = 0;  in set_prot_desc_rx()  local
148 	temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode);  in set_prot_desc_rx()
149 	temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode);  in set_prot_desc_rx()
150 	temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1);  in set_prot_desc_rx()
151 	temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2);  in set_prot_desc_rx()
153 		temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1);  in set_prot_desc_rx()
154 		temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2);  in set_prot_desc_rx()
156 		temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);  in set_prot_desc_rx()
157 		temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);  in set_prot_desc_rx()
160 	temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay);  in set_prot_desc_rx()
161 	temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order);  in set_prot_desc_rx()
162 	temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol);  in set_prot_desc_rx()
163 	temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap);  in set_prot_desc_rx()
164 	temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode);  in set_prot_desc_rx()
165 	temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);  in set_prot_desc_rx()
167 	writel(temp_reg, msp->registers + MSP_RCF);  in set_prot_desc_rx()
175 	u32 temp_reg = 0;  in configure_protocol()  local
204 	temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;  in configure_protocol()
205 	temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol);  in configure_protocol()
206 	writel(temp_reg, msp->registers + MSP_GCR);  in configure_protocol()
207 	temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;  in configure_protocol()
208 	temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol);  in configure_protocol()
209 	writel(temp_reg, msp->registers + MSP_GCR);  in configure_protocol()
220 	u32 temp_reg = 0;  in setup_bitclk()  local
253 	temp_reg = (sck_div - 1) & SCK_DIV_MASK;  in setup_bitclk()
254 	temp_reg |= FRAME_WIDTH_BITS(frame_width);  in setup_bitclk()
255 	temp_reg |= FRAME_PERIOD_BITS(frame_per);  in setup_bitclk()
256 	writel(temp_reg, msp->registers + MSP_SRG);  in setup_bitclk()