Lines Matching refs:msp
115 static void set_prot_desc_tx(struct ux500_msp *msp, in set_prot_desc_tx() argument
125 if (msp->def_elem_len) { in set_prot_desc_tx()
139 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
142 static void set_prot_desc_rx(struct ux500_msp *msp, in set_prot_desc_rx() argument
152 if (msp->def_elem_len) { in set_prot_desc_rx()
167 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
170 static int configure_protocol(struct ux500_msp *msp, in configure_protocol() argument
178 msp->def_elem_len = config->def_elem_len; in configure_protocol()
181 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n", in configure_protocol()
192 dev_err(msp->dev, in configure_protocol()
199 set_prot_desc_tx(msp, protdesc, data_size); in configure_protocol()
201 set_prot_desc_rx(msp, protdesc, data_size); in configure_protocol()
204 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
206 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
207 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
209 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
214 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config) in setup_bitclk() argument
223 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
224 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
247 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n", in setup_bitclk()
256 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
258 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1); in setup_bitclk()
262 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
263 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
269 static int configure_multichannel(struct ux500_msp *msp, in configure_multichannel() argument
278 dev_err(msp->dev, in configure_multichannel()
292 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
295 msp->registers + MSP_MCR); in configure_multichannel()
297 msp->registers + MSP_TCE0); in configure_multichannel()
299 msp->registers + MSP_TCE1); in configure_multichannel()
301 msp->registers + MSP_TCE2); in configure_multichannel()
303 msp->registers + MSP_TCE3); in configure_multichannel()
305 dev_err(msp->dev, in configure_multichannel()
313 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
316 msp->registers + MSP_MCR); in configure_multichannel()
318 msp->registers + MSP_RCE0); in configure_multichannel()
320 msp->registers + MSP_RCE1); in configure_multichannel()
322 msp->registers + MSP_RCE2); in configure_multichannel()
324 msp->registers + MSP_RCE3); in configure_multichannel()
326 dev_err(msp->dev, in configure_multichannel()
332 reg_val_MCR = readl(msp->registers + MSP_MCR); in configure_multichannel()
335 msp->registers + MSP_MCR); in configure_multichannel()
338 msp->registers + MSP_RCM); in configure_multichannel()
340 msp->registers + MSP_RCV); in configure_multichannel()
348 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config) in enable_msp() argument
354 configure_protocol(msp, config); in enable_msp()
355 setup_bitclk(msp, config); in enable_msp()
357 status = configure_multichannel(msp, config); in enable_msp()
359 dev_warn(msp->dev, in enable_msp()
366 !msp->capture_dma_data.dma_cfg) { in enable_msp()
367 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!", in enable_msp()
372 !msp->playback_dma_data.dma_cfg) { in enable_msp()
373 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!", in enable_msp()
378 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in enable_msp()
383 writel(reg_val_DMACR, msp->registers + MSP_DMACR); in enable_msp()
385 writel(config->iodelay, msp->registers + MSP_IODLY); in enable_msp()
388 reg_val_GCR = readl(msp->registers + MSP_GCR); in enable_msp()
389 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); in enable_msp()
394 static void flush_fifo_rx(struct ux500_msp *msp) in flush_fifo_rx() argument
399 reg_val_GCR = readl(msp->registers + MSP_GCR); in flush_fifo_rx()
400 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_rx()
402 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_rx()
404 readl(msp->registers + MSP_DR); in flush_fifo_rx()
405 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_rx()
408 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_rx()
411 static void flush_fifo_tx(struct ux500_msp *msp) in flush_fifo_tx() argument
416 reg_val_GCR = readl(msp->registers + MSP_GCR); in flush_fifo_tx()
417 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_tx()
418 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); in flush_fifo_tx()
420 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_tx()
422 readl(msp->registers + MSP_TSTDR); in flush_fifo_tx()
423 reg_val_FLR = readl(msp->registers + MSP_FLR); in flush_fifo_tx()
425 writel(0x0, msp->registers + MSP_ITCR); in flush_fifo_tx()
426 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_tx()
429 int ux500_msp_i2s_open(struct ux500_msp *msp, in ux500_msp_i2s_open() argument
437 dev_err(msp->dev, in ux500_msp_i2s_open()
446 dev_err(msp->dev, "%s: Error: No direction selected!\n", in ux500_msp_i2s_open()
451 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0; in ux500_msp_i2s_open()
452 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0; in ux500_msp_i2s_open()
454 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__); in ux500_msp_i2s_open()
458 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__); in ux500_msp_i2s_open()
462 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0); in ux500_msp_i2s_open()
477 old_reg = readl(msp->registers + MSP_GCR); in ux500_msp_i2s_open()
480 writel(new_reg, msp->registers + MSP_GCR); in ux500_msp_i2s_open()
482 res = enable_msp(msp, config); in ux500_msp_i2s_open()
484 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n", in ux500_msp_i2s_open()
489 msp->loopback_enable = 1; in ux500_msp_i2s_open()
492 flush_fifo_tx(msp); in ux500_msp_i2s_open()
493 flush_fifo_rx(msp); in ux500_msp_i2s_open()
495 msp->msp_state = MSP_STATE_CONFIGURED; in ux500_msp_i2s_open()
499 static void disable_msp_rx(struct ux500_msp *msp) in disable_msp_rx() argument
503 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp_rx()
504 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); in disable_msp_rx()
505 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in disable_msp_rx()
506 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_rx()
507 reg_val_IMSC = readl(msp->registers + MSP_IMSC); in disable_msp_rx()
510 msp->registers + MSP_IMSC); in disable_msp_rx()
512 msp->dir_busy &= ~MSP_DIR_RX; in disable_msp_rx()
515 static void disable_msp_tx(struct ux500_msp *msp) in disable_msp_tx() argument
519 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp_tx()
520 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); in disable_msp_tx()
521 reg_val_DMACR = readl(msp->registers + MSP_DMACR); in disable_msp_tx()
522 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_tx()
523 reg_val_IMSC = readl(msp->registers + MSP_IMSC); in disable_msp_tx()
526 msp->registers + MSP_IMSC); in disable_msp_tx()
528 msp->dir_busy &= ~MSP_DIR_TX; in disable_msp_tx()
531 static int disable_msp(struct ux500_msp *msp, unsigned int dir) in disable_msp() argument
536 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp()
540 reg_val_GCR = readl(msp->registers + MSP_GCR); in disable_msp()
542 msp->registers + MSP_GCR); in disable_msp()
545 flush_fifo_tx(msp); in disable_msp()
548 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
549 (~TX_ENABLE)), msp->registers + MSP_GCR); in disable_msp()
552 flush_fifo_rx(msp); in disable_msp()
555 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
557 msp->registers + MSP_GCR); in disable_msp()
559 disable_msp_tx(msp); in disable_msp()
560 disable_msp_rx(msp); in disable_msp()
562 disable_msp_tx(msp); in disable_msp()
564 disable_msp_rx(msp); in disable_msp()
569 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction) in ux500_msp_i2s_trigger() argument
573 if (msp->msp_state == MSP_STATE_IDLE) { in ux500_msp_i2s_trigger()
574 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n", in ux500_msp_i2s_trigger()
587 reg_val_GCR = readl(msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
588 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
595 disable_msp_tx(msp); in ux500_msp_i2s_trigger()
597 disable_msp_rx(msp); in ux500_msp_i2s_trigger()
606 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir) in ux500_msp_i2s_close() argument
610 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir); in ux500_msp_i2s_close()
612 status = disable_msp(msp, dir); in ux500_msp_i2s_close()
613 if (msp->dir_busy == 0) { in ux500_msp_i2s_close()
615 msp->msp_state = MSP_STATE_IDLE; in ux500_msp_i2s_close()
616 writel((readl(msp->registers + MSP_GCR) & in ux500_msp_i2s_close()
618 msp->registers + MSP_GCR); in ux500_msp_i2s_close()
620 writel(0, msp->registers + MSP_GCR); in ux500_msp_i2s_close()
621 writel(0, msp->registers + MSP_TCF); in ux500_msp_i2s_close()
622 writel(0, msp->registers + MSP_RCF); in ux500_msp_i2s_close()
623 writel(0, msp->registers + MSP_DMACR); in ux500_msp_i2s_close()
624 writel(0, msp->registers + MSP_SRG); in ux500_msp_i2s_close()
625 writel(0, msp->registers + MSP_MCR); in ux500_msp_i2s_close()
626 writel(0, msp->registers + MSP_RCM); in ux500_msp_i2s_close()
627 writel(0, msp->registers + MSP_RCV); in ux500_msp_i2s_close()
628 writel(0, msp->registers + MSP_TCE0); in ux500_msp_i2s_close()
629 writel(0, msp->registers + MSP_TCE1); in ux500_msp_i2s_close()
630 writel(0, msp->registers + MSP_TCE2); in ux500_msp_i2s_close()
631 writel(0, msp->registers + MSP_TCE3); in ux500_msp_i2s_close()
632 writel(0, msp->registers + MSP_RCE0); in ux500_msp_i2s_close()
633 writel(0, msp->registers + MSP_RCE1); in ux500_msp_i2s_close()
634 writel(0, msp->registers + MSP_RCE2); in ux500_msp_i2s_close()
635 writel(0, msp->registers + MSP_RCE3); in ux500_msp_i2s_close()
643 struct ux500_msp *msp, in ux500_msp_i2s_of_init_msp() argument
655 msp->playback_dma_data.dma_cfg = devm_kzalloc(&pdev->dev, in ux500_msp_i2s_of_init_msp()
658 if (!msp->playback_dma_data.dma_cfg) in ux500_msp_i2s_of_init_msp()
661 msp->capture_dma_data.dma_cfg = devm_kzalloc(&pdev->dev, in ux500_msp_i2s_of_init_msp()
664 if (!msp->capture_dma_data.dma_cfg) in ux500_msp_i2s_of_init_msp()
676 struct ux500_msp *msp; in ux500_msp_i2s_init_msp() local
680 msp = *msp_p; in ux500_msp_i2s_init_msp()
681 if (!msp) in ux500_msp_i2s_init_msp()
686 ret = ux500_msp_i2s_of_init_msp(pdev, msp, in ux500_msp_i2s_init_msp()
693 msp->playback_dma_data.dma_cfg = platform_data->msp_i2s_dma_tx; in ux500_msp_i2s_init_msp()
694 msp->capture_dma_data.dma_cfg = platform_data->msp_i2s_dma_rx; in ux500_msp_i2s_init_msp()
695 msp->id = platform_data->id; in ux500_msp_i2s_init_msp()
698 msp->dev = &pdev->dev; in ux500_msp_i2s_init_msp()
707 msp->playback_dma_data.tx_rx_addr = res->start + MSP_DR; in ux500_msp_i2s_init_msp()
708 msp->capture_dma_data.tx_rx_addr = res->start + MSP_DR; in ux500_msp_i2s_init_msp()
710 msp->registers = devm_ioremap(&pdev->dev, res->start, in ux500_msp_i2s_init_msp()
712 if (msp->registers == NULL) { in ux500_msp_i2s_init_msp()
717 msp->msp_state = MSP_STATE_IDLE; in ux500_msp_i2s_init_msp()
718 msp->loopback_enable = 0; in ux500_msp_i2s_init_msp()
724 struct ux500_msp *msp) in ux500_msp_i2s_cleanup_msp() argument
726 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id); in ux500_msp_i2s_cleanup_msp()