Lines Matching refs:catpt_updatel_pci
168 catpt_updatel_pci(cdev, VDRTCTL0, mask, new); in catpt_dsp_set_srampge()
208 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_update_srampge()
213 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_update_srampge()
246 catpt_updatel_pci(cdev, VDRTCTL0, LPT_VDRTCTL0_APLLSE, val); in lpt_dsp_pll_shutdown()
254 catpt_updatel_pci(cdev, VDRTCTL2, WPT_VDRTCTL2_APLLSE, val); in wpt_dsp_pll_shutdown()
362 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_power_down()
377 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); in catpt_dsp_power_down()
379 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DTCGE, in catpt_dsp_power_down()
388 catpt_updatel_pci(cdev, VDRTCTL0, mask, cdev->spec->d3pgd_bit); in catpt_dsp_power_down()
390 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D3hot); in catpt_dsp_power_down()
395 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_power_down()
407 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, 0); in catpt_dsp_power_up()
412 catpt_updatel_pci(cdev, VDRTCTL2, mask, val); in catpt_dsp_power_up()
414 catpt_updatel_pci(cdev, PMCS, PCI_PM_CTRL_STATE_MASK, PCI_D0); in catpt_dsp_power_up()
418 catpt_updatel_pci(cdev, VDRTCTL0, mask, mask); in catpt_dsp_power_up()
433 catpt_updatel_pci(cdev, VDRTCTL2, CATPT_VDRTCTL2_DCLCGE, in catpt_dsp_power_up()