60 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
62 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
64 	csr.full |= 0x7;  in intel_sst_reset_dsp_mrfld()
65 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in intel_sst_reset_dsp_mrfld()
66 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
68 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
70 	csr.full &= ~(0x1);  in intel_sst_reset_dsp_mrfld()
71 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in intel_sst_reset_dsp_mrfld()
73 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in intel_sst_reset_dsp_mrfld()
74 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in intel_sst_reset_dsp_mrfld()
89 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
90 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in sst_start_mrfld()
92 	csr.full |= 0x7;  in sst_start_mrfld()
93 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in sst_start_mrfld()
95 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
96 	dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full);  in sst_start_mrfld()
99 	csr.full &= ~(0x5);  in sst_start_mrfld()
100 	sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full);  in sst_start_mrfld()
102 	csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR);  in sst_start_mrfld()
104 			csr.full);  in sst_start_mrfld()