44 	s = snd_hdac_stream_assign(azx_bus(chip), substream);  in azx_assign_device()
206 	struct hdac_bus *bus = azx_bus(chip);  in azx_pcm_trigger()
392 		snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);  in azx_get_sync_time()
395 		snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);  in azx_get_sync_time()
398 			if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &  in azx_get_sync_time()
411 		wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);  in azx_get_sync_time()
414 		tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);  in azx_get_sync_time()
415 		tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);  in azx_get_sync_time()
418 		ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);  in azx_get_sync_time()
419 		ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);  in azx_get_sync_time()
422 		snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);  in azx_get_sync_time()
848 			azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);  in azx_single_wait_for_response()
856 	azx_bus(chip)->rirb.res[addr] = -1;  in azx_single_wait_for_response()
945 	struct hdac_bus *bus = azx_bus(chip);  in azx_get_dsp_loader_dev()
1025 	if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {  in azx_init_chip()
1035 	struct hdac_bus *bus = azx_bus(chip);  in azx_stop_all_streams()
1043 	snd_hdac_bus_stop_chip(azx_bus(chip));  in azx_stop_chip()
1067 	struct hdac_bus *bus = azx_bus(chip);  in azx_interrupt()
1131 	struct hdac_bus *bus = azx_bus(chip);  in probe_codec()
1195 	struct hdac_bus *bus = azx_bus(chip);  in azx_probe_codecs()
1306 		snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),  in azx_init_streams()
1316 	struct hdac_bus *bus = azx_bus(chip);  in azx_free_streams()