205 #define BA0_CLKCR1		0x0400	/* Clock Control Register 1 */  macro
1280 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);  in snd_cs4281_free()
1385 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);  in snd_cs4281_chip_init()
1415 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);  in snd_cs4281_chip_init()
1417 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);  in snd_cs4281_chip_init()
1428 		if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)  in snd_cs4281_chip_init()
1931 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);  in cs4281_suspend()
1933 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);  in cs4281_suspend()
1950 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);  in cs4281_suspend()
1955 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);  in cs4281_suspend()
1957 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);  in cs4281_suspend()
1968 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);  in cs4281_resume()
1970 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);  in cs4281_resume()
1982 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);  in cs4281_resume()
1984 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);  in cs4281_resume()