Lines Matching refs:V4L2_INIT_BT_TIMINGS
25 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ macro
28 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ macro
36 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
46 V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
56 V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
67 V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
77 V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
86 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
95 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
104 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
114 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
123 V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
133 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
143 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
152 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
162 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
172 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
181 V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
192 V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
202 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
213 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
223 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
234 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
243 V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
253 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
264 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
273 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
283 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
292 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
305 V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
312 V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
319 V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
329 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
336 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
343 V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
351 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
359 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
367 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
375 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
383 V4L2_INIT_BT_TIMINGS(800, 600, 0, \
391 V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
399 V4L2_INIT_BT_TIMINGS(848, 480, 0, \
407 V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
416 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
423 V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
430 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
438 V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
446 V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
455 V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
466 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
474 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
481 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
488 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
495 V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
503 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
511 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
518 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
525 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
532 V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
540 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
548 V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
556 V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
565 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
573 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
581 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
589 V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
597 V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
605 V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
613 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
621 V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
630 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
638 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
645 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
652 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
659 V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
668 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
676 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
683 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
690 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
697 V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
705 V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
714 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
722 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
730 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
738 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
746 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
754 V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
763 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
771 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
778 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
785 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
792 V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
800 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
807 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
814 V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
822 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
829 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
836 V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
847 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
855 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
862 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
869 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
876 V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
884 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
891 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
898 V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
906 V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
915 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
923 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
930 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
937 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
944 V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
953 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
961 V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
972 V4L2_INIT_BT_TIMINGS(720, 487, 1, \