Lines Matching defs:hdac_bus

289 struct hdac_bus {  struct
291 	const struct hdac_bus_ops *ops;  argument
292 	const struct hdac_ext_bus_ops *ext_ops;
295 	unsigned long addr;
296 	void __iomem *remap_addr;
297 	int irq;
299 	void __iomem *ppcap;
300 	void __iomem *spbcap;
301 	void __iomem *mlcap;
302 	void __iomem *gtscap;
303 	void __iomem *drsmcap;
306 	struct list_head codec_list;
307 	unsigned int num_codecs;
310 	struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
313 	u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
314 	unsigned int unsol_rp, unsol_wp;
315 	struct work_struct unsol_work;
318 	unsigned long codec_mask;
321 	unsigned long codec_powered;
324 	struct hdac_rb corb;
325 	struct hdac_rb rirb;
326 	unsigned int last_cmd[HDA_MAX_CODECS];	/* last sent command */
327 	wait_queue_head_t rirb_wq;
330 	struct snd_dma_buffer rb;
331 	struct snd_dma_buffer posbuf;
332 	int dma_type;			/* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
335 	struct list_head stream_list;
338 	bool chip_init:1;		/* h/w initialized */
341 	bool aligned_mmio:1;		/* aligned MMIO access */
342 	bool sync_write:1;		/* sync after verb write */
343 	bool use_posbuf:1;		/* use position buffer */
344 	bool snoop:1;			/* enable snooping */
345 	bool align_bdle_4k:1;		/* BDLE align 4K boundary */
346 	bool reverse_assign:1;		/* assign devices in reverse order */
347 	bool corbrp_self_clear:1;	/* CORBRP clears itself after reset */
348 	bool polling_mode:1;
349 	bool needs_damn_long_delay:1;
351 	int poll_count;
353 	int bdl_pos_adj;		/* BDL position adjustment */
356 	unsigned int dma_stop_delay;
380 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,  argument