Lines Matching defs:gpmc_device_timings

77 struct gpmc_device_timings {  struct
78 	u32 t_ceasu;	/* address setup to CS valid */
79 	u32 t_avdasu;	/* address setup to ADV valid */
87 	u32 t_avdp_r;	/* ADV low time (what about t_cer ?) */
88 	u32 t_avdp_w;
89 	u32 t_aavdh;	/* address hold time */
90 	u32 t_oeasu;	/* address setup to OE valid */
91 	u32 t_aa;	/* access time from ADV assertion */
92 	u32 t_iaa;	/* initial access time */
93 	u32 t_oe;	/* access time from OE assertion */
94 	u32 t_ce;	/* access time from CS asertion */
95 	u32 t_rd_cycle;	/* read cycle time */
96 	u32 t_cez_r;	/* read CS deassertion to high Z */
97 	u32 t_cez_w;	/* write CS deassertion to high Z */
98 	u32 t_oez;	/* OE deassertion to high Z */
99 	u32 t_weasu;	/* address setup to WE valid */
100 	u32 t_wpl;	/* write assertion time */
101 	u32 t_wph;	/* write deassertion time */
102 	u32 t_wr_cycle;	/* write cycle time */
104 	u32 clk;
105 	u32 t_bacc;	/* burst access valid clock to output delay */
106 	u32 t_ces;	/* CS setup time to clk */
107 	u32 t_avds;	/* ADV setup time to clk */
108 	u32 t_avdh;	/* ADV hold time from clk */
109 	u32 t_ach;	/* address hold time from clk */
110 	u32 t_rdyo;	/* clk to ready valid */
112 	u32 t_ce_rdyz;	/* XXX: description ?, or use t_cez instead */
113 	u32 t_ce_avd;	/* CS on to ADV on delay */
118 	u8 cyc_aavdh_oe;/* read address hold time in cycles */
119 	u8 cyc_aavdh_we;/* write address hold time in cycles */
120 	u8 cyc_oe;	/* access time from OE assertion in cycles */
121 	u8 cyc_wpl;	/* write deassertion time in cycles */
122 	u32 cyc_iaa;	/* initial access time in cycles */
125 	bool ce_xdelay;
126 	bool avd_xdelay;
127 	bool oe_xdelay;
128 	bool we_xdelay;