215 	struct fintek_wdt *wd = watchdog_get_drvdata(wdd);  in fintek_wdt_set_timeout()  local
218 		wd->timer_val = DIV_ROUND_UP(timeout, 60);  in fintek_wdt_set_timeout()
219 		wd->minutes_mode = true;  in fintek_wdt_set_timeout()
220 		timeout = wd->timer_val * 60;  in fintek_wdt_set_timeout()
222 		wd->timer_val = timeout;  in fintek_wdt_set_timeout()
223 		wd->minutes_mode = false;  in fintek_wdt_set_timeout()
231 static int fintek_wdt_set_pulse_width(struct fintek_wdt *wd, unsigned int pw)  in fintek_wdt_set_pulse_width()  argument
235 	if (wd->type == f71868) {  in fintek_wdt_set_pulse_width()
242 		wd->pulse_val = 0;  in fintek_wdt_set_pulse_width()
244 		wd->pulse_val = 1;  in fintek_wdt_set_pulse_width()
246 		wd->pulse_val = 2;  in fintek_wdt_set_pulse_width()
248 		wd->pulse_val = 3;  in fintek_wdt_set_pulse_width()
254 	wd->pulse_mode = pw;  in fintek_wdt_set_pulse_width()
261 	struct fintek_wdt *wd = watchdog_get_drvdata(wdd);  in fintek_wdt_keepalive()  local
264 	err = superio_enter(wd->sioaddr);  in fintek_wdt_keepalive()
267 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_keepalive()
269 	if (wd->minutes_mode)  in fintek_wdt_keepalive()
271 		superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_keepalive()
275 		superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_keepalive()
279 	superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME,  in fintek_wdt_keepalive()
280 			   wd->timer_val);  in fintek_wdt_keepalive()
282 	superio_exit(wd->sioaddr);  in fintek_wdt_keepalive()
289 	struct fintek_wdt *wd = watchdog_get_drvdata(wdd);  in fintek_wdt_start()  local
298 	err = superio_enter(wd->sioaddr);  in fintek_wdt_start()
301 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_start()
304 	switch (wd->type) {  in fintek_wdt_start()
307 		superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT2, 3);  in fintek_wdt_start()
308 		superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 3);  in fintek_wdt_start()
314 			superio_clear_bit(wd->sioaddr, SIO_REG_ROM_ADDR_SEL, 6);  in fintek_wdt_start()
315 			superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT3, 4);  in fintek_wdt_start()
317 			superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);  in fintek_wdt_start()
324 		superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT1, 4);  in fintek_wdt_start()
329 		superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);  in fintek_wdt_start()
334 		superio_outb(wd->sioaddr, SIO_REG_MFUNCT3,  in fintek_wdt_start()
335 			superio_inb(wd->sioaddr, SIO_REG_MFUNCT3) & 0xcf);  in fintek_wdt_start()
340 		superio_clear_bit(wd->sioaddr, SIO_REG_CLOCK_SEL, 3);  in fintek_wdt_start()
342 		superio_outb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f &  in fintek_wdt_start()
343 			superio_inb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL));  in fintek_wdt_start()
348 		superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 5);  in fintek_wdt_start()
359 		tmp = superio_inb(wd->sioaddr, SIO_F81866_REG_PORT_SEL);  in fintek_wdt_start()
362 		superio_outb(wd->sioaddr, SIO_F81866_REG_PORT_SEL, tmp);  in fintek_wdt_start()
364 		superio_clear_bit(wd->sioaddr, SIO_F81866_REG_GPIO1, 5);  in fintek_wdt_start()
376 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_start()
377 	superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0);  in fintek_wdt_start()
379 	if (wd->type == f81865 || wd->type == f81866 || wd->type == f81966)  in fintek_wdt_start()
380 		superio_set_bit(wd->sioaddr, F81865_REG_WDO_CONF,  in fintek_wdt_start()
383 		superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF,  in fintek_wdt_start()
386 	superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_start()
389 	if (wd->pulse_mode) {  in fintek_wdt_start()
391 		u8 wdt_conf = superio_inb(wd->sioaddr,  in fintek_wdt_start()
395 		wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_val & 0x03);  in fintek_wdt_start()
399 		superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_start()
403 		superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_start()
408 	superio_exit(wd->sioaddr);  in fintek_wdt_start()
415 	struct fintek_wdt *wd = watchdog_get_drvdata(wdd);  in fintek_wdt_stop()  local
418 	err = superio_enter(wd->sioaddr);  in fintek_wdt_stop()
421 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_stop()
423 	superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_stop()
426 	superio_exit(wd->sioaddr);  in fintek_wdt_stop()
431 static bool fintek_wdt_is_running(struct fintek_wdt *wd, u8 wdt_conf)  in fintek_wdt_is_running()  argument
433 	return (superio_inb(wd->sioaddr, SIO_REG_ENABLE) & BIT(0))  in fintek_wdt_is_running()
450 	struct fintek_wdt *wd;  in fintek_wdt_probe()  local
461 	wd = devm_kzalloc(dev, sizeof(*wd), GFP_KERNEL);  in fintek_wdt_probe()
462 	if (!wd)  in fintek_wdt_probe()
467 	wd->type = pdata->type;  in fintek_wdt_probe()
468 	wd->sioaddr = sioaddr;  in fintek_wdt_probe()
469 	wd->ident.options = WDIOF_SETTIMEOUT  in fintek_wdt_probe()
474 	snprintf(wd->ident.identity,  in fintek_wdt_probe()
475 		sizeof(wd->ident.identity), "%s watchdog",  in fintek_wdt_probe()
476 		fintek_wdt_names[wd->type]);  in fintek_wdt_probe()
481 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_probe()
492 	wdd = &wd->wdd;  in fintek_wdt_probe()
494 	if (fintek_wdt_is_running(wd, wdt_conf))  in fintek_wdt_probe()
500 	wdd->info               = &wd->ident;  in fintek_wdt_probe()
505 	watchdog_set_drvdata(wdd, wd);  in fintek_wdt_probe()
520 	fintek_wdt_set_pulse_width(wd, pulse_width);  in fintek_wdt_probe()