36 	via_write_reg_mask(VIACR, 0x11, 0x00, 0x80);  in via_set_primary_timing()
41 	via_write_reg_mask(VIACR, 0x03, raw.hor_blank_end & 0x1F, 0x1F);  in via_set_primary_timing()
43 	via_write_reg_mask(VIACR, 0x05, (raw.hor_sync_end & 0x1F)  in via_set_primary_timing()
46 	via_write_reg_mask(VIACR, 0x07, (raw.ver_total >> 8 & 0x01)  in via_set_primary_timing()
53 	via_write_reg_mask(VIACR, 0x09, raw.ver_blank_start >> (9 - 5) & 0x20,  in via_set_primary_timing()
56 	via_write_reg_mask(VIACR, 0x11, raw.ver_sync_end & 0x0F, 0x0F);  in via_set_primary_timing()
60 	via_write_reg_mask(VIACR, 0x33, (raw.hor_sync_start >> (8 - 4) & 0x10)  in via_set_primary_timing()
62 	via_write_reg_mask(VIACR, 0x35, (raw.ver_total >> 10 & 0x01)  in via_set_primary_timing()
66 	via_write_reg_mask(VIACR, 0x36, raw.hor_total >> (8 - 3) & 0x08, 0x08);  in via_set_primary_timing()
69 	via_write_reg_mask(VIACR, 0x11, 0x80, 0x80);  in via_set_primary_timing()
72 	via_write_reg_mask(VIACR, 0x17, 0x00, 0x80);  in via_set_primary_timing()
73 	via_write_reg_mask(VIACR, 0x17, 0x80, 0x80);  in via_set_primary_timing()
100 	via_write_reg_mask(VIACR, 0x55, (raw.hor_total >> 8 & 0x0F)  in via_set_secondary_timing()
127 	via_write_reg_mask(VIACR, 0x48, (addr >> 24) & 0x1F, 0x1F);  in via_set_primary_address()
134 	via_write_reg_mask(VIACR, 0x62, (addr >> 2) & 0xFE, 0xFE);  in via_set_secondary_address()
137 	via_write_reg_mask(VIACR, 0xA3, (addr >> 26) & 0x07, 0x07);  in via_set_secondary_address()
148 	via_write_reg_mask(VIACR, 0x35, (pitch >> (8 - 5)) & 0xE0, 0xE0);  in via_set_primary_pitch()
156 	via_write_reg_mask(VIACR, 0x67, (pitch >> 8) & 0x03, 0x03);  in via_set_secondary_pitch()
157 	via_write_reg_mask(VIACR, 0x71, (pitch >> (10 - 7)) & 0x80, 0x80);  in via_set_secondary_pitch()
187 	via_write_reg_mask(VIASR, 0x15, value, 0x1C);  in via_set_primary_color_depth()
214 	via_write_reg_mask(VIACR, 0x67, value, 0xC0);  in via_set_secondary_color_depth()