118 		BUG();  in DISPC_DEFAULT_COLOR()
135 		BUG();  in DISPC_TRANS_COLOR()
146 		BUG();  in DISPC_TIMING_H()
153 		BUG();  in DISPC_TIMING_H()
164 		BUG();  in DISPC_TIMING_V()
171 		BUG();  in DISPC_TIMING_V()
182 		BUG();  in DISPC_POL_FREQ()
189 		BUG();  in DISPC_POL_FREQ()
200 		BUG();  in DISPC_DIVISORo()
207 		BUG();  in DISPC_DIVISORo()
225 		BUG();  in DISPC_SIZE_MGR()
236 		BUG();  in DISPC_DATA_CYCLE1()
243 		BUG();  in DISPC_DATA_CYCLE1()
254 		BUG();  in DISPC_DATA_CYCLE2()
261 		BUG();  in DISPC_DATA_CYCLE2()
272 		BUG();  in DISPC_DATA_CYCLE3()
279 		BUG();  in DISPC_DATA_CYCLE3()
290 		BUG();  in DISPC_CPR_COEF_R()
297 		BUG();  in DISPC_CPR_COEF_R()
308 		BUG();  in DISPC_CPR_COEF_G()
315 		BUG();  in DISPC_CPR_COEF_G()
326 		BUG();  in DISPC_CPR_COEF_B()
333 		BUG();  in DISPC_CPR_COEF_B()
353 		BUG();  in DISPC_OVL_BASE()
370 		BUG();  in DISPC_BA0_OFFSET()
386 		BUG();  in DISPC_BA1_OFFSET()
395 		BUG();  in DISPC_BA0_UV_OFFSET()
406 		BUG();  in DISPC_BA0_UV_OFFSET()
415 		BUG();  in DISPC_BA1_UV_OFFSET()
426 		BUG();  in DISPC_BA1_UV_OFFSET()
441 		BUG();  in DISPC_POS_OFFSET()
457 		BUG();  in DISPC_SIZE_OFFSET()
474 		BUG();  in DISPC_ATTR_OFFSET()
483 		BUG();  in DISPC_ATTR2_OFFSET()
494 		BUG();  in DISPC_ATTR2_OFFSET()
511 		BUG();  in DISPC_FIFO_THRESH_OFFSET()
528 		BUG();  in DISPC_FIFO_SIZE_STATUS_OFFSET()
545 		BUG();  in DISPC_ROW_INC_OFFSET()
562 		BUG();  in DISPC_PIX_INC_OFFSET()
575 		BUG();  in DISPC_WINDOW_SKIP_OFFSET()
578 		BUG();  in DISPC_WINDOW_SKIP_OFFSET()
591 		BUG();  in DISPC_TABLE_BA_OFFSET()
594 		BUG();  in DISPC_TABLE_BA_OFFSET()
603 		BUG();  in DISPC_FIR_OFFSET()
612 		BUG();  in DISPC_FIR_OFFSET()
621 		BUG();  in DISPC_FIR2_OFFSET()
632 		BUG();  in DISPC_FIR2_OFFSET()
641 		BUG();  in DISPC_PIC_SIZE_OFFSET()
650 		BUG();  in DISPC_PIC_SIZE_OFFSET()
660 		BUG();  in DISPC_ACCU0_OFFSET()
669 		BUG();  in DISPC_ACCU0_OFFSET()
678 		BUG();  in DISPC_ACCU2_0_OFFSET()
689 		BUG();  in DISPC_ACCU2_0_OFFSET()
698 		BUG();  in DISPC_ACCU1_OFFSET()
707 		BUG();  in DISPC_ACCU1_OFFSET()
716 		BUG();  in DISPC_ACCU2_1_OFFSET()
727 		BUG();  in DISPC_ACCU2_1_OFFSET()
737 		BUG();  in DISPC_FIR_COEF_H_OFFSET()
746 		BUG();  in DISPC_FIR_COEF_H_OFFSET()
756 		BUG();  in DISPC_FIR_COEF_H2_OFFSET()
767 		BUG();  in DISPC_FIR_COEF_H2_OFFSET()
777 		BUG();  in DISPC_FIR_COEF_HV_OFFSET()
786 		BUG();  in DISPC_FIR_COEF_HV_OFFSET()
796 		BUG();  in DISPC_FIR_COEF_HV2_OFFSET()
807 		BUG();  in DISPC_FIR_COEF_HV2_OFFSET()
817 		BUG();  in DISPC_CONV_COEF_OFFSET()
825 		BUG();  in DISPC_CONV_COEF_OFFSET()
835 		BUG();  in DISPC_FIR_COEF_V_OFFSET()
845 		BUG();  in DISPC_FIR_COEF_V_OFFSET()
855 		BUG();  in DISPC_FIR_COEF_V2_OFFSET()
866 		BUG();  in DISPC_FIR_COEF_V2_OFFSET()
883 		BUG();  in DISPC_PRELOAD_OFFSET()
902 		BUG();  in DISPC_MFLAG_THRESHOLD_OFFSET()