52 	dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
251 static inline void dispc_write_reg(const u16 idx, u32 val)  in dispc_write_reg()  function
285 	dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
580 	dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);  in dispc_ovl_write_firh_reg()
585 	dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);  in dispc_ovl_write_firhv_reg()
590 	dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);  in dispc_ovl_write_firv_reg()
597 	dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);  in dispc_ovl_write_firh2_reg()
605 	dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);  in dispc_ovl_write_firhv2_reg()
612 	dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);  in dispc_ovl_write_firv2_reg()
666 	dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));  in dispc_ovl_write_color_conv_coef()
667 	dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));  in dispc_ovl_write_color_conv_coef()
668 	dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));  in dispc_ovl_write_color_conv_coef()
669 	dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));  in dispc_ovl_write_color_conv_coef()
670 	dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));  in dispc_ovl_write_color_conv_coef()
699 	dispc_write_reg(DISPC_OVL_BA0(plane), paddr);  in dispc_ovl_set_ba0()
704 	dispc_write_reg(DISPC_OVL_BA1(plane), paddr);  in dispc_ovl_set_ba1()
709 	dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);  in dispc_ovl_set_ba0_uv()
714 	dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);  in dispc_ovl_set_ba1_uv()
727 	dispc_write_reg(DISPC_OVL_POSITION(plane), val);  in dispc_ovl_set_pos()
736 		dispc_write_reg(DISPC_OVL_SIZE(plane), val);  in dispc_ovl_set_input_size()
738 		dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);  in dispc_ovl_set_input_size()
751 		dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);  in dispc_ovl_set_output_size()
753 		dispc_write_reg(DISPC_OVL_SIZE(plane), val);  in dispc_ovl_set_output_size()
800 	dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);  in dispc_ovl_set_pix_inc()
805 	dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);  in dispc_ovl_set_row_inc()
959 	dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);  in dispc_ovl_set_channel_out()
1069 	dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);  in dispc_mgr_set_cpr_coef()
1070 	dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);  in dispc_mgr_set_cpr_coef()
1071 	dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);  in dispc_mgr_set_cpr_coef()
1082 	dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);  in dispc_ovl_set_vid_color_conv()
1106 	dispc_write_reg(DISPC_SIZE_MGR(channel), val);  in dispc_mgr_set_size()
1150 		dispc_write_reg(DISPC_GLOBAL_BUFFER, v);  in dispc_init_fifos()
1219 	dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),  in dispc_ovl_set_fifo_threshold()
1230 		dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));  in dispc_ovl_set_fifo_threshold()
1306 	dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),  in dispc_ovl_set_mflag_threshold()
1324 	dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,  in dispc_init_mflag()
1383 		dispc_write_reg(DISPC_OVL_FIR(plane), val);  in dispc_ovl_set_fir()
1386 		dispc_write_reg(DISPC_OVL_FIR2(plane), val);  in dispc_ovl_set_fir()
1401 	dispc_write_reg(DISPC_OVL_ACCU0(plane), val);  in dispc_ovl_set_vid_accu0()
1415 	dispc_write_reg(DISPC_OVL_ACCU1(plane), val);  in dispc_ovl_set_vid_accu1()
1424 	dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);  in dispc_ovl_set_vid_accu2_0()
1433 	dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);  in dispc_ovl_set_vid_accu2_1()
1575 	dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);  in dispc_ovl_set_scaling_common()
2846 	dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);  in dispc_mgr_set_default_color()
2855 	dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);  in dispc_mgr_set_trans_key()
2941 	dispc_write_reg(DISPC_CONTROL, l);  in dispc_mgr_set_io_pad_mode()
3037 	dispc_write_reg(DISPC_TIMING_H(channel), timing_h);  in _dispc_mgr_set_lcd_timings()
3038 	dispc_write_reg(DISPC_TIMING_V(channel), timing_v);  in _dispc_mgr_set_lcd_timings()
3109 	dispc_write_reg(DISPC_POL_FREQ(channel), l);  in _dispc_mgr_set_lcd_timings()
3180 	dispc_write_reg(DISPC_DIVISORo(channel),  in dispc_mgr_set_lcd_divisor()
3683 	dispc_write_reg(DISPC_IRQSTATUS, mask);  in dispc_clear_irqstatus()
3700 	dispc_write_reg(DISPC_IRQENABLE, mask);  in dispc_write_irqenable()
3724 		dispc_write_reg(DISPC_DIVISOR, l);  in _omap_dispc_initial_config()