Lines Matching refs:NV_RD32
83 NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300)); in NVShowHideCursor()
147 pll = NV_RD32(par->PMC, 0x4020); in nvGetClocks()
149 pll = NV_RD32(par->PMC, 0x4024); in nvGetClocks()
162 pll = NV_RD32(par->PMC, 0x4000); in nvGetClocks()
164 pll = NV_RD32(par->PMC, 0x4004); in nvGetClocks()
172 pll = NV_RD32(par->PRAMDAC0, 0x0504); in nvGetClocks()
176 pll = NV_RD32(par->PRAMDAC0, 0x0574); in nvGetClocks()
186 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nvGetClocks()
190 pll = NV_RD32(par->PRAMDAC0, 0x0570); in nvGetClocks()
202 pll = NV_RD32(par->PRAMDAC0, 0x0504); in nvGetClocks()
215 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nvGetClocks()
228 pll = NV_RD32(par->PRAMDAC0, 0x0504); in nvGetClocks()
234 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nvGetClocks()
391 cfg1 = NV_RD32(par->PFB, 0x00000204); in nv4UpdateArbitrationSettings()
395 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv4UpdateArbitrationSettings()
630 cfg1 = NV_RD32(par->PFB, 0x0204); in nv10UpdateArbitrationSettings()
634 sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0; in nv10UpdateArbitrationSettings()
635 sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ? in nv10UpdateArbitrationSettings()
703 pll = NV_RD32(par->PRAMDAC0, 0x0500); in nForceUpdateArbitrationSettings()
897 state->control = NV_RD32(par->PRAMDAC0, 0x0580) & in NVCalcStateExt()
933 state->config = NV_RD32(par->PFB, 0x00000200); in NVCalcStateExt()
1060 NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000); in NVLoadStateExt()
1062 NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000); in NVLoadStateExt()
1064 NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000); in NVLoadStateExt()
1066 NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000); in NVLoadStateExt()
1068 NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000); in NVLoadStateExt()
1070 NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000); in NVLoadStateExt()
1072 NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000); in NVLoadStateExt()
1074 NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000); in NVLoadStateExt()
1144 NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000); in NVLoadStateExt()
1146 NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000); in NVLoadStateExt()
1148 NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000); in NVLoadStateExt()
1150 NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000); in NVLoadStateExt()
1152 NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000); in NVLoadStateExt()
1154 NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000); in NVLoadStateExt()
1156 NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000); in NVLoadStateExt()
1158 NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000); in NVLoadStateExt()
1166 NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000); in NVLoadStateExt()
1168 NV_RD32(par->PRAMIN, in NVLoadStateExt()
1194 NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00); in NVLoadStateExt()
1196 NV_RD32(par->PGRAPH, 0x0710) | 0x00020100); in NVLoadStateExt()
1205 NV_RD32(&par->PFB[(0x0240 / 4) + i], in NVLoadStateExt()
1222 NV_RD32(par->PGRAPH, 0x0bc4) | in NVLoadStateExt()
1225 j = NV_RD32(par->REGS, 0x1540) & 0xff; in NVLoadStateExt()
1252 NV_RD32(par->PFB, 0x33C) & in NVLoadStateExt()
1267 NV_RD32(par->PFB, 0x020C)); in NVLoadStateExt()
1271 NV_RD32(par->PFB, 0x020C)); in NVLoadStateExt()
1275 NV_RD32(par->PRAMDAC, in NVLoadStateExt()
1288 NV_RD32(par->PRAMDAC, 0x0608) | in NVLoadStateExt()
1295 NV_RD32(par->PRAMDAC, 0x0608) | in NVLoadStateExt()
1363 NV_RD32(par->PFB, 0x0240 +i*4)); in NVLoadStateExt()
1365 NV_RD32(par->PFB, 0x0240 +i*4)); in NVLoadStateExt()
1376 NV_RD32(par->PFB, in NVLoadStateExt()
1380 NV_RD32(par->PFB, in NVLoadStateExt()
1387 NV_RD32(par->PFB, in NVLoadStateExt()
1397 NV_RD32(par->PFB, in NVLoadStateExt()
1406 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1408 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1410 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1412 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1426 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1428 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1431 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1433 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1436 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1438 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1449 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1451 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1454 NV_RD32(par->PFB, 0x0200)); in NVLoadStateExt()
1457 NV_RD32(par->PFB, 0x0204)); in NVLoadStateExt()
1522 NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) | in NVLoadStateExt()
1644 state->vpll = NV_RD32(par->PRAMDAC0, 0x0508); in NVUnloadStateExt()
1646 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); in NVUnloadStateExt()
1648 state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578); in NVUnloadStateExt()
1649 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); in NVUnloadStateExt()
1651 state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C); in NVUnloadStateExt()
1652 state->general = NV_RD32(par->PRAMDAC, 0x0600); in NVUnloadStateExt()
1653 state->scale = NV_RD32(par->PRAMDAC, 0x0848); in NVUnloadStateExt()
1654 state->config = NV_RD32(par->PFB, 0x0200); in NVUnloadStateExt()
1657 state->control = NV_RD32(par->PRAMDAC0, 0x0580); in NVUnloadStateExt()
1661 state->head = NV_RD32(par->PCRTC0, 0x0860); in NVUnloadStateExt()
1662 state->head2 = NV_RD32(par->PCRTC0, 0x2860); in NVUnloadStateExt()
1668 state->cursorConfig = NV_RD32(par->PCRTC, 0x0810); in NVUnloadStateExt()
1671 state->dither = NV_RD32(par->PRAMDAC, 0x0528); in NVUnloadStateExt()
1673 state->dither = NV_RD32(par->PRAMDAC, 0x083C); in NVUnloadStateExt()