Lines Matching refs:PPLL_REF_DIV
623 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { in radeon_probe_pll_params()
647 m = (INPLL(PPLL_REF_DIV) & 0x3ff); in radeon_probe_pll_params()
689 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; in radeon_probe_pll_params()
768 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()
1343 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()
1362 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
1401 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
1404 OUTPLLP(PPLL_REF_DIV, in radeon_write_pll_regs()
1409 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
1416 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) in radeon_write_pll_regs()
1418 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); in radeon_write_pll_regs()
1425 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) in radeon_write_pll_regs()