Lines Matching refs:aty_st_le32
549 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) macro
573 aty_st_le32(CLOCK_CNTL_DATA, val); in _aty_st_pll()
618 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); in register_test()
620 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); in register_test()
626 aty_st_le32(BIOS_0_SCRATCH, val); // restore value in register_test()
684 aty_st_le32(PC_NGUI_CTLSTAT, tmp); in aty128_flush_pixel_cache()
704 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); in aty128_reset_engine()
706 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); in aty128_reset_engine()
710 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); in aty128_reset_engine()
711 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); in aty128_reset_engine()
714 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); in aty128_reset_engine()
728 aty_st_le32(SCALE_3D_CNTL, 0x00000000); in aty128_init_engine()
739 aty_st_le32(DEFAULT_OFFSET, 0x00000000); in aty128_init_engine()
742 aty_st_le32(DEFAULT_PITCH, pitch_value); in aty128_init_engine()
745 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); in aty128_init_engine()
748 aty_st_le32(DP_GUI_MASTER_CNTL, in aty128_init_engine()
767 aty_st_le32(DST_BRES_ERR, 0); in aty128_init_engine()
768 aty_st_le32(DST_BRES_INC, 0); in aty128_init_engine()
769 aty_st_le32(DST_BRES_DEC, 0); in aty128_init_engine()
772 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
773 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
776 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ in aty128_init_engine()
777 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ in aty128_init_engine()
780 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); in aty128_init_engine()
823 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); in aty128_map_ROM()
1019 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); in aty128_set_crtc()
1020 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); in aty128_set_crtc()
1021 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); in aty128_set_crtc()
1022 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); in aty128_set_crtc()
1023 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); in aty128_set_crtc()
1024 aty_st_le32(CRTC_PITCH, crtc->pitch); in aty128_set_crtc()
1025 aty_st_le32(CRTC_OFFSET, crtc->offset); in aty128_set_crtc()
1026 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); in aty128_set_crtc()
1282 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | in aty128_set_crt_enable()
1284 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | in aty128_set_crt_enable()
1287 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & in aty128_set_crt_enable()
1302 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1312 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1315 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_set_lcd_enable()
1330 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); in aty128_set_pll()
1419 aty_st_le32(DDA_CONFIG, dsp->dda_config); in aty128_set_fifo()
1420 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); in aty128_set_fifo()
1497 aty_st_le32(OVR_CLR, 0); in aty128fb_set_par()
1498 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); in aty128fb_set_par()
1499 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); in aty128fb_set_par()
1500 aty_st_le32(OV0_SCALE_CNTL, 0); in aty128fb_set_par()
1501 aty_st_le32(MPP_TB_CONFIG, 0); in aty128fb_set_par()
1502 aty_st_le32(MPP_GP_CONFIG, 0); in aty128fb_set_par()
1503 aty_st_le32(SUBPIC_CNTL, 0); in aty128fb_set_par()
1504 aty_st_le32(VIPH_CONTROL, 0); in aty128fb_set_par()
1505 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ in aty128fb_set_par()
1506 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ in aty128fb_set_par()
1507 aty_st_le32(CAP0_TRIG_CNTL, 0); in aty128fb_set_par()
1508 aty_st_le32(CAP1_TRIG_CNTL, 0); in aty128fb_set_par()
1525 aty_st_le32(CNFG_CNTL, config); in aty128fb_set_par()
1645 aty_st_le32(CRTC_OFFSET, offset); in aty128fb_pan_display()
1658 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & in aty128_st_pal()
1663 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); in aty128_st_pal()
1781 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1785 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1794 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1796 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); in aty128_bl_update_status()
1804 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1809 aty_st_le32(LVDS_GEN_CNTL, reg); in aty128_bl_update_status()
1811 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); in aty128_bl_update_status()
2017 aty_st_le32(DAC_CNTL, dac); in aty128_init()
2020 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); in aty128_init()
2351 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & in aty128_set_suspend()
2359 aty_st_le32(BUS_CNTL1, 0x00000010); in aty128_set_suspend()
2360 aty_st_le32(MEM_POWER_MISC, 0x0c830000); in aty128_set_suspend()