88 	musb_writel(&rx->rx_skipbytes, 0, 0);  in cppi_reset_rx()
89 	musb_writel(&rx->rx_head, 0, 0);  in cppi_reset_rx()
90 	musb_writel(&rx->rx_sop, 0, 0);  in cppi_reset_rx()
91 	musb_writel(&rx->rx_current, 0, 0);  in cppi_reset_rx()
92 	musb_writel(&rx->rx_buf_current, 0, 0);  in cppi_reset_rx()
93 	musb_writel(&rx->rx_len_len, 0, 0);  in cppi_reset_rx()
94 	musb_writel(&rx->rx_cnt_cnt, 0, 0);  in cppi_reset_rx()
100 	musb_writel(&tx->tx_head, 0, 0);  in cppi_reset_tx()
101 	musb_writel(&tx->tx_buf, 0, 0);  in cppi_reset_tx()
102 	musb_writel(&tx->tx_current, 0, 0);  in cppi_reset_tx()
103 	musb_writel(&tx->tx_buf_current, 0, 0);  in cppi_reset_tx()
104 	musb_writel(&tx->tx_info, 0, 0);  in cppi_reset_tx()
105 	musb_writel(&tx->tx_rem_len, 0, 0);  in cppi_reset_tx()
107 	musb_writel(&tx->tx_complete, 0, ptr);  in cppi_reset_tx()
202 	musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,  in cppi_controller_start()
204 	musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG,  in cppi_controller_start()
208 	musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);  in cppi_controller_start()
209 	musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);  in cppi_controller_start()
212 	musb_writel(tibase, DAVINCI_RNDIS_REG, 0);  in cppi_controller_start()
213 	musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0);  in cppi_controller_start()
232 	musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,  in cppi_controller_stop()
234 	musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,  in cppi_controller_stop()
251 	musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);  in cppi_controller_stop()
252 	musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);  in cppi_controller_stop()
265 	musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8));  in core_rxirq_disable()
270 	musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8));  in core_rxirq_enable()
424 		musb_writel(tibase, DAVINCI_RNDIS_REG, value);  in cppi_rndis_update()
484 		musb_writel(tibase, DAVINCI_AUTOREQ_REG, val);  in cppi_autoreq_update()
664 	musb_writel(&tx_ram->tx_head, 0, (u32)tx->freelist->dma);  in cppi_next_tx_segment()
903 	musb_writel(&rx_ram->rx_head, 0, bd->dma);  in cppi_next_rx_segment()
914 		musb_writel(tibase,  in cppi_next_rx_segment()
918 		musb_writel(tibase,  in cppi_next_rx_segment()
928 		musb_writel(tibase,  in cppi_next_rx_segment()
1067 			musb_writel(&state->rx_complete, 0, safe2ack);  in cppi_rx_scan()
1090 			musb_writel(&state->rx_complete, 0, safe2ack);  in cppi_rx_scan()
1195 			musb_writel(&tx_ram->tx_complete, 0, 0);  in cppi_interrupt()
1227 				musb_writel(&tx_ram->tx_complete, 0, bd->dma);  in cppi_interrupt()
1289 	musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);  in cppi_interrupt()
1427 		musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index);  in cppi_channel_abort()
1453 		musb_writel(&tx_ram->tx_complete, 0, 1);  in cppi_channel_abort()
1475 			musb_writel(tibase, DAVINCI_AUTOREQ_REG, value);  in cppi_channel_abort()