Lines Matching refs:temp
258 u16 temp; in xhci_common_hub_descriptor() local
263 temp = 0; in xhci_common_hub_descriptor()
266 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
268 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
271 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
274 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
282 u16 temp; in xhci_usb2_hub_descriptor() local
292 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
661 u32 temp; in xhci_set_port_power() local
665 temp = readl(port->addr); in xhci_set_port_power()
668 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
670 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
674 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
678 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
682 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
684 if (temp) in xhci_set_port_power()
693 u32 temp; in xhci_port_set_test_mode() local
698 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
699 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
700 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
772 u32 temp; in xhci_set_link_state() local
776 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
777 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
778 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
779 writel(temp, port->addr); in xhci_set_link_state()
783 portsc, temp); in xhci_set_link_state()
789 u32 temp; in xhci_set_remote_wake_mask() local
791 temp = readl(port->addr); in xhci_set_remote_wake_mask()
792 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
795 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
797 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
800 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
802 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
805 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
807 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
809 writel(temp, port->addr); in xhci_set_remote_wake_mask()
816 u32 temp; in xhci_test_and_clear_bit() local
818 temp = readl(port->addr); in xhci_test_and_clear_bit()
819 if (temp & port_bit) { in xhci_test_and_clear_bit()
820 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
821 temp |= port_bit; in xhci_test_and_clear_bit()
822 writel(temp, port->addr); in xhci_test_and_clear_bit()
1188 u32 temp, status; in xhci_hub_control() local
1239 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1240 if (temp == ~(u32)0) { in xhci_hub_control()
1245 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1246 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1252 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1265 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1282 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1283 if (temp == ~(u32)0) { in xhci_hub_control()
1288 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1292 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1293 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1305 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1306 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1307 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1330 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1334 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1339 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1344 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1347 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1348 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1358 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1382 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1392 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1396 if (!(temp & PORT_PE)) { in xhci_hub_control()
1416 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1442 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1462 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1463 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1467 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1481 temp = (temp | PORT_RESET); in xhci_hub_control()
1482 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1484 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1486 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1491 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1493 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1496 temp |= PORT_WR; in xhci_hub_control()
1497 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1498 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1503 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1504 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1505 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1506 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1511 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1512 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1513 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1514 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1530 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1536 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1537 if (temp == ~(u32)0) { in xhci_hub_control()
1543 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1546 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1548 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1549 if (temp & PORT_RESET) in xhci_hub_control()
1551 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1552 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1588 ports[wIndex]->addr, temp); in xhci_hub_control()
1592 ports[wIndex]->addr, temp); in xhci_hub_control()
1624 u32 temp, status; in xhci_hub_status_data() local
1666 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1667 if (temp == ~(u32)0) { in xhci_hub_status_data()
1672 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1674 if ((temp & mask) != 0 || in xhci_hub_status_data()
1681 if ((temp & PORT_RC)) in xhci_hub_status_data()
1683 if (temp & PORT_OC) in xhci_hub_status_data()
1865 u32 temp, portsc; in xhci_bus_resume() local
1884 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1885 temp &= ~CMD_EIE; in xhci_bus_resume()
1886 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1963 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1964 temp |= CMD_EIE; in xhci_bus_resume()
1965 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1966 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()