Lines Matching refs:UIC_ARG_MIB_SEL
237 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i), in exynosauto_ufs_pre_link()
239 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0); in exynosauto_ufs_pre_link()
241 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i), in exynosauto_ufs_pre_link()
243 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i), in exynosauto_ufs_pre_link()
245 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i), in exynosauto_ufs_pre_link()
248 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79); in exynosauto_ufs_pre_link()
249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1); in exynosauto_ufs_pre_link()
250 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6); in exynosauto_ufs_pre_link()
254 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i), in exynosauto_ufs_pre_link()
257 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i), in exynosauto_ufs_pre_link()
260 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i), in exynosauto_ufs_pre_link()
262 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i), in exynosauto_ufs_pre_link()
264 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i), in exynosauto_ufs_pre_link()
268 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1); in exynosauto_ufs_pre_link()
315 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17); in exynos7_ufs_pre_link()
317 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff); in exynos7_ufs_pre_link()
318 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00); in exynos7_ufs_pre_link()
324 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0); in exynos7_ufs_pre_link()
344 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83); in exynos7_ufs_post_link()
345 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07); in exynos7_ufs_post_link()
346 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i), in exynos7_ufs_post_link()
575 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i), in exynos_ufs_config_phy_time_attr()
577 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i), in exynos_ufs_config_phy_time_attr()
579 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
581 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
583 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
585 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
587 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
589 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
594 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i), in exynos_ufs_config_phy_time_attr()
596 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i), in exynos_ufs_config_phy_time_attr()
598 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i), in exynos_ufs_config_phy_time_attr()
600 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
602 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i), in exynos_ufs_config_phy_time_attr()
604 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i), in exynos_ufs_config_phy_time_attr()
606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i), in exynos_ufs_config_phy_time_attr()
608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i), in exynos_ufs_config_phy_time_attr()
611 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i), in exynos_ufs_config_phy_time_attr()
628 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
631 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
634 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
637 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
640 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
643 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i), in exynos_ufs_config_phy_cap_attr()
650 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0); in exynos_ufs_config_phy_cap_attr()
654 UIC_ARG_MIB_SEL( in exynos_ufs_config_phy_cap_attr()
660 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i), in exynos_ufs_config_phy_cap_attr()
667 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, in exynos_ufs_config_phy_cap_attr()
673 UIC_ARG_MIB_SEL( in exynos_ufs_config_phy_cap_attr()
679 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP, in exynos_ufs_config_phy_cap_attr()
757 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask); in exynos_ufs_config_sync_pattern_mask()
1480 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), in fsd_ufs_pre_link()
1482 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); in fsd_ufs_pre_link()
1486 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), in fsd_ufs_pre_link()
1488 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); in fsd_ufs_pre_link()
1489 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); in fsd_ufs_pre_link()
1490 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); in fsd_ufs_pre_link()
1491 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); in fsd_ufs_pre_link()
1492 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); in fsd_ufs_pre_link()
1493 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); in fsd_ufs_pre_link()
1514 ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), in fsd_ufs_post_link()
1533 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); in fsd_ufs_post_link()
1534 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); in fsd_ufs_post_link()
1535 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); in fsd_ufs_post_link()
1536 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); in fsd_ufs_post_link()