29 		{ UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
30 		{ UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
31 		{ UIC_ARG_MIB(CDIRECTCTRL6), 0x80, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
32 		{ UIC_ARG_MIB(CBDIVFACTOR), 0x08, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
33 		{ UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
34 		{ UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
35 		{ UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
52 		{ UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
53 		{ UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
76 		{ UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_40bit_rmmi()
109 		{ UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
110 		{ UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
129 		{ UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi_lane0()
190 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),  in tc_dwc_g210_setup_20bit_rmmi_lane1()
192 	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),  in tc_dwc_g210_setup_20bit_rmmi_lane1()
225 		{ UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
226 		{ UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
227 		{ UIC_ARG_MIB(CDIRECTCTRL6), 0xc0, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
228 		{ UIC_ARG_MIB(CBDIVFACTOR), 0x44, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
229 		{ UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
230 		{ UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
231 		{ UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },  in tc_dwc_g210_setup_20bit_rmmi()
273 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);  in tc_dwc_g210_config_40_bit()
278 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);  in tc_dwc_g210_config_40_bit()
305 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);  in tc_dwc_g210_config_20_bit()
310 	ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);  in tc_dwc_g210_config_20_bit()