398 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
400 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
405 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1328 	wr_reg16(info, TCR, value);  in set_break()
2064 	wr_reg16(info, SSR, status); /* clear pending */  in isr_serial()
2204 		wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in isr_txeom()
2205 		wr_reg16(info, TCR, val); /* clear reset bit */  in isr_txeom()
2634 			wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);  in rx_enable()
2687 			wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));  in wait_mgsl_event()
2750 			wr_reg16(info, SCR,  in wait_mgsl_event()
2786 	wr_reg16(info, TCR, val);  in set_interface()
3769 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)  in wr_reg16()  function
3821 	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));  in enable_loopback()
3860 		wr_reg16(info, BDR, (unsigned short)div);  in set_rate()
3870 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_stop()
3871 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_stop()
3876 	wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);  in rx_stop()
3891 	wr_reg16(info, SSR, IRQ_RXOVER);  in rx_start()
3895 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_start()
3896 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_start()
3903 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));  in rx_start()
3911 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));  in rx_start()
3927 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
3936 		wr_reg16(info, TCR,  in tx_start()
3957 			wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_start()
3962 			wr_reg16(info, SSR, IRQ_TXIDLE);  in tx_start()
3981 	wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in tx_stop()
3986 	wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_stop()
4067 	wr_reg16(info, TCR, val);  in async_mode()
4104 	wr_reg16(info, RCR, val);  in async_mode()
4150 	wr_reg16(info, SCR, val);  in async_mode()
4229 	wr_reg16(info, TCR, val);  in sync_mode()
4292 	wr_reg16(info, RCR, val);  in sync_mode()
4343 		wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));  in sync_mode()
4374 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);  in sync_mode()
4401 	wr_reg16(info, TCR, tcr);  in tx_set_idle()
4862 		wr_reg16(info, TIR, patterns[i]);  in register_test()
4863 		wr_reg16(info, BDR, patterns[(i+1)%count]);  in register_test()
4890 	wr_reg16(info, TCR,  in irq_test()
4894 	wr_reg16(info, TDR, 0);  in irq_test()