Lines Matching refs:TCR
365 #define TCR 0x82 /* tx control */ macro
1323 value = rd_reg16(info, TCR); in set_break()
1328 wr_reg16(info, TCR, value); in set_break()
2203 unsigned short val = rd_reg16(info, TCR); in isr_txeom()
2204 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2205 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2781 val = rd_reg16(info, TCR); in set_interface()
2786 wr_reg16(info, TCR, val); in set_interface()
3936 wr_reg16(info, TCR, in tx_start()
3937 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
3980 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
3981 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in tx_stop()
4067 wr_reg16(info, TCR, val); in async_mode()
4229 wr_reg16(info, TCR, val); in sync_mode()
4391 tcr = rd_reg16(info, TCR); in tx_set_idle()
4401 wr_reg16(info, TCR, tcr); in tx_set_idle()
4890 wr_reg16(info, TCR, in irq_test()
4891 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()