Lines Matching refs:se
126 struct geni_se se; member
203 port->se.base = uport->membase; in qcom_geni_serial_request_port()
491 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_console_write()
494 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_console_write()
627 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_stop_tx()
630 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_stop_tx()
648 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); in qcom_geni_serial_start_rx()
679 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx()
873 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); in setup_fifos()
874 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); in setup_fifos()
875 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); in setup_fifos()
904 proto = geni_se_read_proto(&port->se); in qcom_geni_serial_port_setup()
937 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, in qcom_geni_serial_port_setup()
939 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); in qcom_geni_serial_port_setup()
940 geni_se_select_mode(&port->se, GENI_SE_FIFO); in qcom_geni_serial_port_setup()
1047 ver = geni_se_get_qup_hw_version(&port->se); in qcom_geni_serial_set_termios()
1051 clk_rate = get_clk_div_rate(port->se.clk, baud, in qcom_geni_serial_set_termios()
1054 dev_err(port->se.dev, in qcom_geni_serial_set_termios()
1060 dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n", in qcom_geni_serial_set_termios()
1074 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; in qcom_geni_serial_set_termios()
1075 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); in qcom_geni_serial_set_termios()
1076 geni_icc_set_bw(&port->se); in qcom_geni_serial_set_termios()
1208 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, in qcom_geni_serial_enable_early_read() argument
1211 geni_se_setup_s_cmd(se, UART_START_READ, 0); in qcom_geni_serial_enable_early_read()
1215 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, in qcom_geni_serial_enable_early_read() argument
1231 struct geni_se se; in qcom_geni_serial_earlycon_setup() local
1238 memset(&se, 0, sizeof(se)); in qcom_geni_serial_earlycon_setup()
1239 se.base = uport->membase; in qcom_geni_serial_earlycon_setup()
1240 if (geni_se_read_proto(&se) != GENI_SE_UART) in qcom_geni_serial_earlycon_setup()
1255 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, in qcom_geni_serial_earlycon_setup()
1257 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); in qcom_geni_serial_earlycon_setup()
1258 geni_se_select_mode(&se, GENI_SE_FIFO); in qcom_geni_serial_earlycon_setup()
1270 qcom_geni_serial_enable_early_read(&se, dev->con); in qcom_geni_serial_earlycon_setup()
1332 geni_icc_enable(&port->se); in qcom_geni_serial_pm()
1333 geni_se_resources_on(&port->se); in qcom_geni_serial_pm()
1336 geni_se_resources_off(&port->se); in qcom_geni_serial_pm()
1337 geni_icc_disable(&port->se); in qcom_geni_serial_pm()
1414 port->se.dev = &pdev->dev; in qcom_geni_serial_probe()
1415 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); in qcom_geni_serial_probe()
1416 port->se.clk = devm_clk_get(&pdev->dev, "se"); in qcom_geni_serial_probe()
1417 if (IS_ERR(port->se.clk)) { in qcom_geni_serial_probe()
1418 ret = PTR_ERR(port->se.clk); in qcom_geni_serial_probe()
1439 ret = geni_icc_get(&port->se, NULL); in qcom_geni_serial_probe()
1442 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; in qcom_geni_serial_probe()
1443 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in qcom_geni_serial_probe()
1446 ret = geni_icc_set_bw(&port->se); in qcom_geni_serial_probe()
1543 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); in qcom_geni_serial_sys_suspend()
1544 geni_icc_set_bw(&port->se); in qcom_geni_serial_sys_suspend()
1558 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); in qcom_geni_serial_sys_resume()
1559 geni_icc_set_bw(&port->se); in qcom_geni_serial_sys_resume()