62 	return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?  in mcf_tx_empty()
73 	sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?  in mcf_get_mctrl()
91 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);  in mcf_set_mctrl()
93 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);  in mcf_set_mctrl()
104 		writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);  in mcf_start_tx()
106 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);  in mcf_start_tx()
109 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_start_tx()
119 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_stop_tx()
129 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_stop_rx()
140 		writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);  in mcf_break_ctl()
142 		writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);  in mcf_break_ctl()
156 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);  in mcf_startup()
157 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);  in mcf_startup()
161 		port->membase + MCFUART_UCR);  in mcf_startup()
165 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_startup()
183 	writeb(pp->imr, port->membase + MCFUART_UIMR);  in mcf_shutdown()
186 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);  in mcf_shutdown()
187 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);  in mcf_shutdown()
262 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);  in mcf_set_termios()
263 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);  in mcf_set_termios()
264 	writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);  in mcf_set_termios()
265 	writeb(mr1, port->membase + MCFUART_UMR);  in mcf_set_termios()
266 	writeb(mr2, port->membase + MCFUART_UMR);  in mcf_set_termios()
267 	writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);  in mcf_set_termios()
268 	writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);  in mcf_set_termios()
270 	writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);  in mcf_set_termios()
273 		port->membase + MCFUART_UCSR);  in mcf_set_termios()
275 		port->membase + MCFUART_UCR);  in mcf_set_termios()
286 	while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {  in mcf_rx_chars()
287 		ch = readb(port->membase + MCFUART_URB);  in mcf_rx_chars()
293 				port->membase + MCFUART_UCR);  in mcf_rx_chars()
334 		writeb(port->x_char, port->membase + MCFUART_UTB);  in mcf_tx_chars()
340 	while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {  in mcf_tx_chars()
343 		writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);  in mcf_tx_chars()
356 				port->membase + MCFUART_UCR);  in mcf_tx_chars()
369 	isr = readb(port->membase + MCFUART_UISR) & pp->imr;  in mcf_interrupt()
393 	writeb(0, port->membase + MCFUART_UIMR);  in mcf_config_port()
440 	mr1 = readb(port->membase + MCFUART_UMR);  in mcf_config_rs485()
441 	mr2 = readb(port->membase + MCFUART_UMR);  in mcf_config_rs485()
450 	writeb(mr1, port->membase + MCFUART_UMR);  in mcf_config_rs485()
451 	writeb(mr2, port->membase + MCFUART_UMR);  in mcf_config_rs485()
502 		port->membase = (platp[i].membase) ? platp[i].membase :  in early_mcf_setup()
524 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)  in mcf_console_putc()
527 	writeb(c, port->membase + MCFUART_UTB);  in mcf_console_putc()
529 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)  in mcf_console_putc()
558 	if (port->membase == 0)  in mcf_console_setup()
628 		port->membase = (platp[i].membase) ? platp[i].membase :  in mcf_probe()