Lines Matching refs:pc
19 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
20 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
21 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
22 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
26 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) in pcicore_read32() argument
28 return ssb_read32(pc->dev, offset); in pcicore_read32()
32 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value) in pcicore_write32() argument
34 ssb_write32(pc->dev, offset, value); in pcicore_write32()
38 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset) in pcicore_read16() argument
40 return ssb_read16(pc->dev, offset); in pcicore_read16()
44 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value) in pcicore_write16() argument
46 ssb_write16(pc->dev, offset, value); in pcicore_write16()
71 static u32 get_cfgspace_addr(struct ssb_pcicore *pc, in get_cfgspace_addr() argument
79 if (pc->cardbusmode && (dev > 1)) in get_cfgspace_addr()
89 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp); in get_cfgspace_addr()
97 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, in get_cfgspace_addr()
110 static int ssb_extpci_read_config(struct ssb_pcicore *pc, in ssb_extpci_read_config() argument
119 WARN_ON(!pc->hostmode); in ssb_extpci_read_config()
122 addr = get_cfgspace_addr(pc, bus, dev, func, off); in ssb_extpci_read_config()
156 static int ssb_extpci_write_config(struct ssb_pcicore *pc, in ssb_extpci_write_config() argument
165 WARN_ON(!pc->hostmode); in ssb_extpci_write_config()
168 addr = get_cfgspace_addr(pc, bus, dev, func, off); in ssb_extpci_write_config()
320 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) in ssb_pcicore_init_hostmode() argument
326 extpci_core = pc; in ssb_pcicore_init_hostmode()
328 dev_dbg(pc->dev->dev, "PCIcore in host mode found\n"); in ssb_pcicore_init_hostmode()
332 pcicore_write32(pc, SSB_PCICORE_CTL, val); in ssb_pcicore_init_hostmode()
334 pcicore_write32(pc, SSB_PCICORE_CTL, val); in ssb_pcicore_init_hostmode()
337 pcicore_write32(pc, SSB_PCICORE_CTL, val); in ssb_pcicore_init_hostmode()
339 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); in ssb_pcicore_init_hostmode()
342 if (pc->dev->bus->has_cardbus_slot) { in ssb_pcicore_init_hostmode()
343 dev_dbg(pc->dev->dev, "CardBus slot detected\n"); in ssb_pcicore_init_hostmode()
344 pc->cardbusmode = 1; in ssb_pcicore_init_hostmode()
346 ssb_gpio_out(pc->dev->bus, 1, 1); in ssb_pcicore_init_hostmode()
347 ssb_gpio_outen(pc->dev->bus, 1, 1); in ssb_pcicore_init_hostmode()
348 pcicore_write16(pc, SSB_PCICORE_SPROM(0), in ssb_pcicore_init_hostmode()
349 pcicore_read16(pc, SSB_PCICORE_SPROM(0)) in ssb_pcicore_init_hostmode()
354 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, in ssb_pcicore_init_hostmode()
357 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, in ssb_pcicore_init_hostmode()
360 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, in ssb_pcicore_init_hostmode()
375 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); in ssb_pcicore_init_hostmode()
378 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); in ssb_pcicore_init_hostmode()
381 pcicore_write32(pc, SSB_PCICORE_IMASK, in ssb_pcicore_init_hostmode()
397 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) in pcicore_is_in_hostmode() argument
399 struct ssb_bus *bus = pc->dev->bus; in pcicore_is_in_hostmode()
423 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE))); in pcicore_is_in_hostmode()
431 static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc) in ssb_pcicore_fix_sprom_core_index() argument
433 u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0)); in ssb_pcicore_fix_sprom_core_index()
434 if (((tmp & 0xF000) >> 12) != pc->dev->core_index) { in ssb_pcicore_fix_sprom_core_index()
436 tmp |= (pc->dev->core_index << 12); in ssb_pcicore_fix_sprom_core_index()
437 pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp); in ssb_pcicore_fix_sprom_core_index()
441 static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc) in ssb_pcicore_polarity_workaround() argument
443 return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; in ssb_pcicore_polarity_workaround()
446 static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc) in ssb_pcicore_serdes_workaround() argument
452 ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, in ssb_pcicore_serdes_workaround()
453 ssb_pcicore_polarity_workaround(pc)); in ssb_pcicore_serdes_workaround()
454 tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); in ssb_pcicore_serdes_workaround()
456 ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); in ssb_pcicore_serdes_workaround()
459 static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc) in ssb_pcicore_pci_setup_workarounds() argument
461 struct ssb_device *pdev = pc->dev; in ssb_pcicore_pci_setup_workarounds()
465 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); in ssb_pcicore_pci_setup_workarounds()
468 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); in ssb_pcicore_pci_setup_workarounds()
479 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); in ssb_pcicore_pci_setup_workarounds()
481 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); in ssb_pcicore_pci_setup_workarounds()
485 static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc) in ssb_pcicore_pcie_setup_workarounds() argument
488 u8 rev = pc->dev->id.revision; in ssb_pcicore_pcie_setup_workarounds()
492 tmp = ssb_pcie_read(pc, 0x4); in ssb_pcicore_pcie_setup_workarounds()
494 ssb_pcie_write(pc, 0x4, tmp); in ssb_pcicore_pcie_setup_workarounds()
498 tmp = ssb_pcie_read(pc, 0x100); in ssb_pcicore_pcie_setup_workarounds()
500 ssb_pcie_write(pc, 0x100, tmp); in ssb_pcicore_pcie_setup_workarounds()
506 ssb_pcie_mdio_write(pc, serdes_rx_device, in ssb_pcicore_pcie_setup_workarounds()
508 ssb_pcie_mdio_write(pc, serdes_rx_device, in ssb_pcicore_pcie_setup_workarounds()
510 ssb_pcie_mdio_write(pc, serdes_rx_device, in ssb_pcicore_pcie_setup_workarounds()
514 ssb_pcicore_serdes_workaround(pc); in ssb_pcicore_pcie_setup_workarounds()
522 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5)); in ssb_pcicore_pcie_setup_workarounds()
524 pcicore_write16(pc, SSB_PCICORE_SPROM(5), in ssb_pcicore_pcie_setup_workarounds()
533 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) in ssb_pcicore_init_clientmode() argument
535 struct ssb_device *pdev = pc->dev; in ssb_pcicore_init_clientmode()
539 ssb_pcicore_fix_sprom_core_index(pc); in ssb_pcicore_init_clientmode()
545 if (pc->dev->id.coreid == SSB_DEV_PCIE) { in ssb_pcicore_init_clientmode()
546 ssb_pcicore_serdes_workaround(pc); in ssb_pcicore_init_clientmode()
552 void ssb_pcicore_init(struct ssb_pcicore *pc) in ssb_pcicore_init() argument
554 struct ssb_device *dev = pc->dev; in ssb_pcicore_init()
562 pc->hostmode = pcicore_is_in_hostmode(pc); in ssb_pcicore_init()
563 if (pc->hostmode) in ssb_pcicore_init()
564 ssb_pcicore_init_hostmode(pc); in ssb_pcicore_init()
566 if (!pc->hostmode) in ssb_pcicore_init()
567 ssb_pcicore_init_clientmode(pc); in ssb_pcicore_init()
570 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) in ssb_pcie_read() argument
572 pcicore_write32(pc, 0x130, address); in ssb_pcie_read()
573 return pcicore_read32(pc, 0x134); in ssb_pcie_read()
576 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data) in ssb_pcie_write() argument
578 pcicore_write32(pc, 0x130, address); in ssb_pcie_write()
579 pcicore_write32(pc, 0x134, data); in ssb_pcie_write()
582 static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) in ssb_pcie_mdio_set_phy() argument
594 pcicore_write32(pc, mdio_data, v); in ssb_pcie_mdio_set_phy()
598 v = pcicore_read32(pc, mdio_control); in ssb_pcie_mdio_set_phy()
605 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) in ssb_pcie_mdio_read() argument
616 pcicore_write32(pc, mdio_control, v); in ssb_pcie_mdio_read()
618 if (pc->dev->id.revision >= 10) { in ssb_pcie_mdio_read()
620 ssb_pcie_mdio_set_phy(pc, device); in ssb_pcie_mdio_read()
626 if (pc->dev->id.revision < 10) in ssb_pcie_mdio_read()
629 pcicore_write32(pc, mdio_data, v); in ssb_pcie_mdio_read()
633 v = pcicore_read32(pc, mdio_control); in ssb_pcie_mdio_read()
636 ret = pcicore_read32(pc, mdio_data); in ssb_pcie_mdio_read()
641 pcicore_write32(pc, mdio_control, 0); in ssb_pcie_mdio_read()
645 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, in ssb_pcie_mdio_write() argument
656 pcicore_write32(pc, mdio_control, v); in ssb_pcie_mdio_write()
658 if (pc->dev->id.revision >= 10) { in ssb_pcie_mdio_write()
660 ssb_pcie_mdio_set_phy(pc, device); in ssb_pcie_mdio_write()
666 if (pc->dev->id.revision < 10) in ssb_pcie_mdio_write()
670 pcicore_write32(pc, mdio_data, v); in ssb_pcie_mdio_write()
674 v = pcicore_read32(pc, mdio_control); in ssb_pcie_mdio_write()
679 pcicore_write32(pc, mdio_control, 0); in ssb_pcie_mdio_write()
682 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, in ssb_pcicore_dev_irqvecs_enable() argument
685 struct ssb_device *pdev = pc->dev; in ssb_pcicore_dev_irqvecs_enable()
730 if (pc->setup_done) in ssb_pcicore_dev_irqvecs_enable()
733 ssb_pcicore_pci_setup_workarounds(pc); in ssb_pcicore_dev_irqvecs_enable()
736 ssb_pcicore_pcie_setup_workarounds(pc); in ssb_pcicore_dev_irqvecs_enable()
738 pc->setup_done = 1; in ssb_pcicore_dev_irqvecs_enable()