75 	struct geni_se se;  member
109 	ret = geni_se_clk_freq_match(&mas->se,  in get_spi_clk_cfg()
137 	struct geni_se *se = &mas->se;  in handle_fifo_timeout()  local
141 	writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in handle_fifo_timeout()
143 	geni_se_cancel_m_cmd(se);  in handle_fifo_timeout()
152 	geni_se_abort_m_cmd(se);  in handle_fifo_timeout()
193 	struct geni_se *se = &mas->se;  in spi_geni_is_abort_still_pending()  local
206 	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);  in spi_geni_is_abort_still_pending()
207 	m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);  in spi_geni_is_abort_still_pending()
229 	struct geni_se *se = &mas->se;  in spi_geni_set_cs()  local
255 		geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);  in spi_geni_set_cs()
257 		geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);  in spi_geni_set_cs()
275 	struct geni_se *se = &mas->se;  in spi_setup_word_len()  local
286 	geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,  in spi_setup_word_len()
289 	writel(word_len, se->base + SE_SPI_WORD_LEN);  in spi_setup_word_len()
296 	struct geni_se *se = &mas->se;  in geni_spi_set_clock_and_bw()  local
319 	writel(clk_sel, se->base + SE_GENI_CLK_SEL);  in geni_spi_set_clock_and_bw()
320 	writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);  in geni_spi_set_clock_and_bw()
323 	se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);  in geni_spi_set_clock_and_bw()
324 	ret = geni_icc_set_bw(se);  in geni_spi_set_clock_and_bw()
335 	struct geni_se *se = &mas->se;  in setup_fifo_params()  local
356 		writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);  in setup_fifo_params()
357 		writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);  in setup_fifo_params()
358 		writel(cpha, se->base + SE_SPI_CPHA);  in setup_fifo_params()
359 		writel(cpol, se->base + SE_SPI_CPOL);  in setup_fifo_params()
360 		writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);  in setup_fifo_params()
556 	struct geni_se *se = &mas->se;  in spi_geni_init()  local
563 	proto = geni_se_read_proto(se);  in spi_geni_init()
568 	mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);  in spi_geni_init()
571 	mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);  in spi_geni_init()
577 	geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);  in spi_geni_init()
580 	ver = geni_se_get_qup_hw_version(se);  in spi_geni_init()
589 	fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;  in spi_geni_init()
595 			geni_se_select_mode(se, GENI_GPI_DMA);  in spi_geni_init()
608 		geni_se_select_mode(se, GENI_SE_FIFO);  in spi_geni_init()
614 	spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);  in spi_geni_init()
616 	writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);  in spi_geni_init()
639 	struct geni_se *se = &mas->se;  in geni_spi_handle_tx()  local
647 		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_handle_tx()
665 		iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);  in geni_spi_handle_tx()
669 		writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_handle_tx()
677 	struct geni_se *se = &mas->se;  in geni_spi_handle_rx()  local
685 	rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);  in geni_spi_handle_rx()
697 			readl(se->base + SE_GENI_RX_FIFOn);  in geni_spi_handle_rx()
712 		ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);  in geni_spi_handle_rx()
725 	struct geni_se *se = &mas->se;  in setup_fifo_xfer()  local
766 		writel(len, se->base + SE_SPI_TX_TRANS_LEN);  in setup_fifo_xfer()
771 		writel(len, se->base + SE_SPI_RX_TRANS_LEN);  in setup_fifo_xfer()
780 	geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);  in setup_fifo_xfer()
783 			writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);  in setup_fifo_xfer()
812 	struct geni_se *se = &mas->se;  in geni_spi_isr()  local
815 	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);  in geni_spi_isr()
850 				writel(0, se->base + SE_GENI_TX_WATERMARK_REG);  in geni_spi_isr()
880 	writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);  in geni_spi_isr()
920 	mas->se.dev = dev;  in spi_geni_probe()
921 	mas->se.wrapper = dev_get_drvdata(dev->parent);  in spi_geni_probe()
922 	mas->se.base = base;  in spi_geni_probe()
923 	mas->se.clk = clk;  in spi_geni_probe()
957 	ret = geni_icc_get(&mas->se, NULL);  in spi_geni_probe()
961 	mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);  in spi_geni_probe()
962 	mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;  in spi_geni_probe()
964 	ret = geni_icc_set_bw(&mas->se);  in spi_geni_probe()
1022 	ret = geni_se_resources_off(&mas->se);  in spi_geni_runtime_suspend()
1026 	return geni_icc_disable(&mas->se);  in spi_geni_runtime_suspend()
1035 	ret = geni_icc_enable(&mas->se);  in spi_geni_runtime_resume()
1039 	ret = geni_se_resources_on(&mas->se);  in spi_geni_runtime_resume()