278 static inline int needs_swap_endian(struct fsl_qspi *q)  in needs_swap_endian()  argument
280 	return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN;  in needs_swap_endian()
283 static inline int needs_4x_clock(struct fsl_qspi *q)  in needs_4x_clock()  argument
285 	return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK;  in needs_4x_clock()
288 static inline int needs_fill_txfifo(struct fsl_qspi *q)  in needs_fill_txfifo()  argument
290 	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890;  in needs_fill_txfifo()
293 static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)  in needs_wakeup_wait_mode()  argument
295 	return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618;  in needs_wakeup_wait_mode()
298 static inline int needs_amba_base_offset(struct fsl_qspi *q)  in needs_amba_base_offset()  argument
300 	return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);  in needs_amba_base_offset()
303 static inline int needs_tdh_setting(struct fsl_qspi *q)  in needs_tdh_setting()  argument
305 	return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;  in needs_tdh_setting()
312 static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)  in fsl_qspi_endian_xchg()  argument
314 	return needs_swap_endian(q) ? __swab32(a) : a;  in fsl_qspi_endian_xchg()
324 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)  in qspi_writel()  argument
326 	if (q->devtype_data->little_endian)  in qspi_writel()
332 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)  in qspi_readl()  argument
334 	if (q->devtype_data->little_endian)  in qspi_readl()
342 	struct fsl_qspi *q = dev_id;  in fsl_qspi_irq_handler()  local
346 	reg = qspi_readl(q, q->iobase + QUADSPI_FR);  in fsl_qspi_irq_handler()
347 	qspi_writel(q, reg, q->iobase + QUADSPI_FR);  in fsl_qspi_irq_handler()
350 		complete(&q->c);  in fsl_qspi_irq_handler()
352 	dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", 0, reg);  in fsl_qspi_irq_handler()
356 static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width)  in fsl_qspi_check_buswidth()  argument
371 	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);  in fsl_qspi_supports_op()  local
374 	ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth);  in fsl_qspi_supports_op()
377 		ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth);  in fsl_qspi_supports_op()
380 		ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth);  in fsl_qspi_supports_op()
383 		ret |= fsl_qspi_check_buswidth(q, op->data.buswidth);  in fsl_qspi_supports_op()
404 	    (op->data.nbytes > q->devtype_data->ahb_buf_size ||  in fsl_qspi_supports_op()
405 	     (op->data.nbytes > q->devtype_data->rxfifo - 4 &&  in fsl_qspi_supports_op()
410 	    op->data.nbytes > q->devtype_data->txfifo)  in fsl_qspi_supports_op()
416 static void fsl_qspi_prepare_lut(struct fsl_qspi *q,  in fsl_qspi_prepare_lut()  argument
419 	void __iomem *base = q->iobase;  in fsl_qspi_prepare_lut()
460 	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);  in fsl_qspi_prepare_lut()
461 	qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);  in fsl_qspi_prepare_lut()
465 		qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));  in fsl_qspi_prepare_lut()
468 	qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);  in fsl_qspi_prepare_lut()
469 	qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);  in fsl_qspi_prepare_lut()
472 static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)  in fsl_qspi_clk_prep_enable()  argument
476 	ret = clk_prepare_enable(q->clk_en);  in fsl_qspi_clk_prep_enable()
480 	ret = clk_prepare_enable(q->clk);  in fsl_qspi_clk_prep_enable()
482 		clk_disable_unprepare(q->clk_en);  in fsl_qspi_clk_prep_enable()
486 	if (needs_wakeup_wait_mode(q))  in fsl_qspi_clk_prep_enable()
487 		cpu_latency_qos_add_request(&q->pm_qos_req, 0);  in fsl_qspi_clk_prep_enable()
492 static void fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)  in fsl_qspi_clk_disable_unprep()  argument
494 	if (needs_wakeup_wait_mode(q))  in fsl_qspi_clk_disable_unprep()
495 		cpu_latency_qos_remove_request(&q->pm_qos_req);  in fsl_qspi_clk_disable_unprep()
497 	clk_disable_unprepare(q->clk);  in fsl_qspi_clk_disable_unprep()
498 	clk_disable_unprepare(q->clk_en);  in fsl_qspi_clk_disable_unprep()
508 static void fsl_qspi_invalidate(struct fsl_qspi *q)  in fsl_qspi_invalidate()  argument
512 	reg = qspi_readl(q, q->iobase + QUADSPI_MCR);  in fsl_qspi_invalidate()
514 	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);  in fsl_qspi_invalidate()
523 	qspi_writel(q, reg, q->iobase + QUADSPI_MCR);  in fsl_qspi_invalidate()
526 static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)  in fsl_qspi_select_mem()  argument
531 	if (q->selected == spi->chip_select)  in fsl_qspi_select_mem()
534 	if (needs_4x_clock(q))  in fsl_qspi_select_mem()
537 	fsl_qspi_clk_disable_unprep(q);  in fsl_qspi_select_mem()
539 	ret = clk_set_rate(q->clk, rate);  in fsl_qspi_select_mem()
543 	ret = fsl_qspi_clk_prep_enable(q);  in fsl_qspi_select_mem()
547 	q->selected = spi->chip_select;  in fsl_qspi_select_mem()
549 	fsl_qspi_invalidate(q);  in fsl_qspi_select_mem()
552 static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)  in fsl_qspi_read_ahb()  argument
555 		      q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size,  in fsl_qspi_read_ahb()
559 static void fsl_qspi_fill_txfifo(struct fsl_qspi *q,  in fsl_qspi_fill_txfifo()  argument
562 	void __iomem *base = q->iobase;  in fsl_qspi_fill_txfifo()
568 		val = fsl_qspi_endian_xchg(q, val);  in fsl_qspi_fill_txfifo()
569 		qspi_writel(q, val, base + QUADSPI_TBDR);  in fsl_qspi_fill_txfifo()
574 		val = fsl_qspi_endian_xchg(q, val);  in fsl_qspi_fill_txfifo()
575 		qspi_writel(q, val, base + QUADSPI_TBDR);  in fsl_qspi_fill_txfifo()
578 	if (needs_fill_txfifo(q)) {  in fsl_qspi_fill_txfifo()
580 			qspi_writel(q, 0, base + QUADSPI_TBDR);  in fsl_qspi_fill_txfifo()
584 static void fsl_qspi_read_rxfifo(struct fsl_qspi *q,  in fsl_qspi_read_rxfifo()  argument
587 	void __iomem *base = q->iobase;  in fsl_qspi_read_rxfifo()
593 		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));  in fsl_qspi_read_rxfifo()
594 		val = fsl_qspi_endian_xchg(q, val);  in fsl_qspi_read_rxfifo()
599 		val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));  in fsl_qspi_read_rxfifo()
600 		val = fsl_qspi_endian_xchg(q, val);  in fsl_qspi_read_rxfifo()
605 static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op)  in fsl_qspi_do_op()  argument
607 	void __iomem *base = q->iobase;  in fsl_qspi_do_op()
610 	init_completion(&q->c);  in fsl_qspi_do_op()
617 	qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT),  in fsl_qspi_do_op()
621 	if (!wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000)))  in fsl_qspi_do_op()
625 		fsl_qspi_read_rxfifo(q, op);  in fsl_qspi_do_op()
630 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,  in fsl_qspi_readl_poll_tout()  argument
635 	if (!q->devtype_data->little_endian)  in fsl_qspi_readl_poll_tout()
644 	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);  in fsl_qspi_exec_op()  local
645 	void __iomem *base = q->iobase;  in fsl_qspi_exec_op()
648 	int invalid_mstrid = q->devtype_data->invalid_mstrid;  in fsl_qspi_exec_op()
650 	mutex_lock(&q->lock);  in fsl_qspi_exec_op()
653 	fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |  in fsl_qspi_exec_op()
656 	fsl_qspi_select_mem(q, mem->spi);  in fsl_qspi_exec_op()
658 	if (needs_amba_base_offset(q))  in fsl_qspi_exec_op()
659 		addr_offset = q->memmap_phy;  in fsl_qspi_exec_op()
661 	qspi_writel(q,  in fsl_qspi_exec_op()
662 		    q->selected * q->devtype_data->ahb_buf_size + addr_offset,  in fsl_qspi_exec_op()
665 	qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |  in fsl_qspi_exec_op()
669 	qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,  in fsl_qspi_exec_op()
672 	qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);  in fsl_qspi_exec_op()
673 	qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);  in fsl_qspi_exec_op()
674 	qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);  in fsl_qspi_exec_op()
676 	fsl_qspi_prepare_lut(q, op);  in fsl_qspi_exec_op()
683 	if (op->data.nbytes > (q->devtype_data->rxfifo - 4) &&  in fsl_qspi_exec_op()
685 		fsl_qspi_read_ahb(q, op);  in fsl_qspi_exec_op()
687 		qspi_writel(q, QUADSPI_RBCT_WMRK_MASK |  in fsl_qspi_exec_op()
691 			fsl_qspi_fill_txfifo(q, op);  in fsl_qspi_exec_op()
693 		err = fsl_qspi_do_op(q, op);  in fsl_qspi_exec_op()
697 	fsl_qspi_invalidate(q);  in fsl_qspi_exec_op()
699 	mutex_unlock(&q->lock);  in fsl_qspi_exec_op()
706 	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);  in fsl_qspi_adjust_op_size()  local
709 		if (op->data.nbytes > q->devtype_data->txfifo)  in fsl_qspi_adjust_op_size()
710 			op->data.nbytes = q->devtype_data->txfifo;  in fsl_qspi_adjust_op_size()
712 		if (op->data.nbytes > q->devtype_data->ahb_buf_size)  in fsl_qspi_adjust_op_size()
713 			op->data.nbytes = q->devtype_data->ahb_buf_size;  in fsl_qspi_adjust_op_size()
714 		else if (op->data.nbytes > (q->devtype_data->rxfifo - 4))  in fsl_qspi_adjust_op_size()
721 static int fsl_qspi_default_setup(struct fsl_qspi *q)  in fsl_qspi_default_setup()  argument
723 	void __iomem *base = q->iobase;  in fsl_qspi_default_setup()
728 	fsl_qspi_clk_disable_unprep(q);  in fsl_qspi_default_setup()
731 	ret = clk_set_rate(q->clk, 66000000);  in fsl_qspi_default_setup()
735 	ret = fsl_qspi_clk_prep_enable(q);  in fsl_qspi_default_setup()
740 	qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,  in fsl_qspi_default_setup()
745 	qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,  in fsl_qspi_default_setup()
753 	if (needs_tdh_setting(q))  in fsl_qspi_default_setup()
754 		qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &  in fsl_qspi_default_setup()
758 	reg = qspi_readl(q, base + QUADSPI_SMPR);  in fsl_qspi_default_setup()
759 	qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK  in fsl_qspi_default_setup()
765 	qspi_writel(q, 0, base + QUADSPI_BUF0IND);  in fsl_qspi_default_setup()
766 	qspi_writel(q, 0, base + QUADSPI_BUF1IND);  in fsl_qspi_default_setup()
767 	qspi_writel(q, 0, base + QUADSPI_BUF2IND);  in fsl_qspi_default_setup()
769 	qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT),  in fsl_qspi_default_setup()
770 		    q->iobase + QUADSPI_BFGENCR);  in fsl_qspi_default_setup()
771 	qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);  in fsl_qspi_default_setup()
772 	qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |  in fsl_qspi_default_setup()
773 		    QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8),  in fsl_qspi_default_setup()
776 	if (needs_amba_base_offset(q))  in fsl_qspi_default_setup()
777 		addr_offset = q->memmap_phy;  in fsl_qspi_default_setup()
786 	qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset,  in fsl_qspi_default_setup()
788 	qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset,  in fsl_qspi_default_setup()
790 	qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset,  in fsl_qspi_default_setup()
792 	qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset,  in fsl_qspi_default_setup()
795 	q->selected = -1;  in fsl_qspi_default_setup()
798 	qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,  in fsl_qspi_default_setup()
802 	qspi_writel(q, 0xffffffff, q->iobase + QUADSPI_FR);  in fsl_qspi_default_setup()
805 	qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);  in fsl_qspi_default_setup()
812 	struct fsl_qspi *q = spi_controller_get_devdata(mem->spi->master);  in fsl_qspi_get_name()  local
821 	if (of_get_available_child_count(q->dev->of_node) == 1)  in fsl_qspi_get_name()
822 		return dev_name(q->dev);  in fsl_qspi_get_name()
825 			      "%s-%d", dev_name(q->dev),  in fsl_qspi_get_name()
849 	struct fsl_qspi *q;  in fsl_qspi_probe()  local
852 	ctlr = spi_alloc_master(&pdev->dev, sizeof(*q));  in fsl_qspi_probe()
859 	q = spi_controller_get_devdata(ctlr);  in fsl_qspi_probe()
860 	q->dev = dev;  in fsl_qspi_probe()
861 	q->devtype_data = of_device_get_match_data(dev);  in fsl_qspi_probe()
862 	if (!q->devtype_data) {  in fsl_qspi_probe()
867 	platform_set_drvdata(pdev, q);  in fsl_qspi_probe()
870 	q->iobase = devm_platform_ioremap_resource_byname(pdev, "QuadSPI");  in fsl_qspi_probe()
871 	if (IS_ERR(q->iobase)) {  in fsl_qspi_probe()
872 		ret = PTR_ERR(q->iobase);  in fsl_qspi_probe()
882 	q->memmap_phy = res->start;  in fsl_qspi_probe()
884 	q->ahb_addr = devm_ioremap(dev, q->memmap_phy,  in fsl_qspi_probe()
885 				   (q->devtype_data->ahb_buf_size * 4));  in fsl_qspi_probe()
886 	if (!q->ahb_addr) {  in fsl_qspi_probe()
892 	q->clk_en = devm_clk_get(dev, "qspi_en");  in fsl_qspi_probe()
893 	if (IS_ERR(q->clk_en)) {  in fsl_qspi_probe()
894 		ret = PTR_ERR(q->clk_en);  in fsl_qspi_probe()
898 	q->clk = devm_clk_get(dev, "qspi");  in fsl_qspi_probe()
899 	if (IS_ERR(q->clk)) {  in fsl_qspi_probe()
900 		ret = PTR_ERR(q->clk);  in fsl_qspi_probe()
904 	ret = fsl_qspi_clk_prep_enable(q);  in fsl_qspi_probe()
916 			fsl_qspi_irq_handler, 0, pdev->name, q);  in fsl_qspi_probe()
922 	mutex_init(&q->lock);  in fsl_qspi_probe()
928 	fsl_qspi_default_setup(q);  in fsl_qspi_probe()
939 	mutex_destroy(&q->lock);  in fsl_qspi_probe()
942 	fsl_qspi_clk_disable_unprep(q);  in fsl_qspi_probe()
953 	struct fsl_qspi *q = platform_get_drvdata(pdev);  in fsl_qspi_remove()  local
956 	qspi_writel(q, QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);  in fsl_qspi_remove()
957 	qspi_writel(q, 0x0, q->iobase + QUADSPI_RSER);  in fsl_qspi_remove()
959 	fsl_qspi_clk_disable_unprep(q);  in fsl_qspi_remove()
961 	mutex_destroy(&q->lock);  in fsl_qspi_remove()
973 	struct fsl_qspi *q = dev_get_drvdata(dev);  in fsl_qspi_resume()  local
975 	fsl_qspi_default_setup(q);  in fsl_qspi_resume()