1358 	uint64_t off8, val, mem_crb, word[2] = {0, 0};  in qla4_82xx_pci_mem_read_2M()  local
1365 		mem_crb = QLA82XX_CRB_QDR_NET;  in qla4_82xx_pci_mem_read_2M()
1367 		mem_crb = QLA82XX_CRB_DDR_NET;  in qla4_82xx_pci_mem_read_2M()
1385 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);  in qla4_82xx_pci_mem_read_2M()
1387 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);  in qla4_82xx_pci_mem_read_2M()
1389 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_read_2M()
1391 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_read_2M()
1394 			temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);  in qla4_82xx_pci_mem_read_2M()
1410 				mem_crb + MIU_TEST_AGT_RDDATA(k));  in qla4_82xx_pci_mem_read_2M()
1449 	uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};  in qla4_82xx_pci_mem_write_2M()  local
1455 		mem_crb = QLA82XX_CRB_QDR_NET;  in qla4_82xx_pci_mem_write_2M()
1457 		mem_crb = QLA82XX_CRB_DDR_NET;  in qla4_82xx_pci_mem_write_2M()
1510 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);  in qla4_82xx_pci_mem_write_2M()
1512 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);  in qla4_82xx_pci_mem_write_2M()
1514 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);  in qla4_82xx_pci_mem_write_2M()
1516 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);  in qla4_82xx_pci_mem_write_2M()
1518 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,  in qla4_82xx_pci_mem_write_2M()
1521 		qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,  in qla4_82xx_pci_mem_write_2M()
1525 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_write_2M()
1527 		qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);  in qla4_82xx_pci_mem_write_2M()
1530 			temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);  in qla4_82xx_pci_mem_write_2M()