Lines Matching refs:tmp
31 u32 tmp; in mvs_64xx_enable_xmt() local
33 tmp = mr32(MVS_PCS); in mvs_64xx_enable_xmt()
35 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT); in mvs_64xx_enable_xmt()
37 tmp |= 1 << (phy_id + PCS_EN_PORT_XMT_SHIFT2); in mvs_64xx_enable_xmt()
38 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt()
70 u32 reg, tmp; in mvs_64xx_stp_reset() local
81 tmp = reg; in mvs_64xx_stp_reset()
83 tmp |= (1U << phy_id) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
85 tmp |= (1U << (phy_id - MVS_SOC_PORTS)) << PCTL_LINK_OFFS; in mvs_64xx_stp_reset()
89 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_stp_reset()
93 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_stp_reset()
98 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_stp_reset()
106 u32 tmp; in mvs_64xx_phy_reset() local
107 tmp = mvs_read_port_irq_stat(mvi, phy_id); in mvs_64xx_phy_reset()
108 tmp &= ~PHYEV_RDY_CH; in mvs_64xx_phy_reset()
109 mvs_write_port_irq_stat(mvi, phy_id, tmp); in mvs_64xx_phy_reset()
110 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_reset()
112 tmp |= PHY_RST_HARD; in mvs_64xx_phy_reset()
114 tmp |= PHY_RST; in mvs_64xx_phy_reset()
115 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_64xx_phy_reset()
118 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_reset()
119 } while (tmp & PHY_RST_HARD); in mvs_64xx_phy_reset()
127 u32 tmp; in mvs_64xx_clear_srs_irq() local
129 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_64xx_clear_srs_irq()
130 if (tmp) { in mvs_64xx_clear_srs_irq()
131 printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp); in mvs_64xx_clear_srs_irq()
132 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_clear_srs_irq()
135 tmp = mr32(MVS_INT_STAT_SRS_0); in mvs_64xx_clear_srs_irq()
136 if (tmp & (1 << (reg_set % 32))) { in mvs_64xx_clear_srs_irq()
147 u32 tmp; in mvs_64xx_chip_reset() local
152 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()
155 if (!(tmp & HBA_RST)) { in mvs_64xx_chip_reset()
157 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); in mvs_64xx_chip_reset()
158 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_chip_reset()
159 tmp |= PCTL_PHY_DSBL; in mvs_64xx_chip_reset()
160 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_chip_reset()
162 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); in mvs_64xx_chip_reset()
163 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_chip_reset()
164 tmp |= PCTL_PHY_DSBL; in mvs_64xx_chip_reset()
165 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_chip_reset()
171 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_chip_reset()
174 if (!(tmp & HBA_RST)) { in mvs_64xx_chip_reset()
197 u32 tmp; in mvs_64xx_phy_disable() local
206 pci_read_config_dword(mvi->pdev, offs, &tmp); in mvs_64xx_phy_disable()
207 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); in mvs_64xx_phy_disable()
208 pci_write_config_dword(mvi->pdev, offs, tmp); in mvs_64xx_phy_disable()
210 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_phy_disable()
211 tmp |= 1U << (PCTL_PHY_DSBL_OFFS + phy_id); in mvs_64xx_phy_disable()
212 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_phy_disable()
219 u32 tmp; in mvs_64xx_phy_enable() local
228 pci_read_config_dword(mvi->pdev, offs, &tmp); in mvs_64xx_phy_enable()
229 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); in mvs_64xx_phy_enable()
230 pci_write_config_dword(mvi->pdev, offs, tmp); in mvs_64xx_phy_enable()
232 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_phy_enable()
233 tmp &= ~(1U << (PCTL_PHY_DSBL_OFFS + phy_id)); in mvs_64xx_phy_enable()
234 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_phy_enable()
242 u32 tmp, cctl; in mvs_64xx_init() local
248 tmp = mvs_64xx_chip_reset(mvi); in mvs_64xx_init()
249 if (tmp) in mvs_64xx_init()
250 return tmp; in mvs_64xx_init()
252 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_init()
253 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_init()
254 tmp |= PCTL_PHY_DSBL; in mvs_64xx_init()
255 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
268 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp); in mvs_64xx_init()
269 tmp &= ~PRD_REQ_MASK; in mvs_64xx_init()
270 tmp |= PRD_REQ_SIZE; in mvs_64xx_init()
271 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp); in mvs_64xx_init()
273 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); in mvs_64xx_init()
274 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_init()
275 tmp &= ~PCTL_PHY_DSBL; in mvs_64xx_init()
276 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_init()
278 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); in mvs_64xx_init()
279 tmp &= PCTL_PWR_OFF; in mvs_64xx_init()
280 tmp &= ~PCTL_PHY_DSBL; in mvs_64xx_init()
281 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_init()
283 tmp = mr32(MVS_PHY_CTL); in mvs_64xx_init()
284 tmp &= ~PCTL_PWR_OFF; in mvs_64xx_init()
285 tmp |= PCTL_COM_ON; in mvs_64xx_init()
286 tmp &= ~PCTL_PHY_DSBL; in mvs_64xx_init()
287 tmp |= PCTL_LINK_RST; in mvs_64xx_init()
288 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
290 tmp &= ~PCTL_LINK_RST; in mvs_64xx_init()
291 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
300 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21); in mvs_64xx_init()
301 tmp &= 0x0000ffff; in mvs_64xx_init()
302 tmp |= 0x00fa0000; in mvs_64xx_init()
303 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp); in mvs_64xx_init()
347 tmp = mvs_read_port_irq_stat(mvi, i); in mvs_64xx_init()
348 tmp &= ~PHYEV_SIG_FIS; in mvs_64xx_init()
349 mvs_write_port_irq_stat(mvi, i, tmp); in mvs_64xx_init()
352 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS | in mvs_64xx_init()
355 mvs_write_port_irq_mask(mvi, i, tmp); in mvs_64xx_init()
370 tmp = mr32(MVS_PCS); in mvs_64xx_init()
371 tmp |= PCS_CMD_RST; in mvs_64xx_init()
372 tmp &= ~PCS_SELF_CLEAR; in mvs_64xx_init()
373 mw32(MVS_PCS, tmp); in mvs_64xx_init()
378 tmp = 0; in mvs_64xx_init()
384 tmp = 0x10000 | interrupt_coalescing; in mvs_64xx_init()
385 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_64xx_init()
396 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM | CINT_SRS | CINT_CI_STOP | in mvs_64xx_init()
399 mw32(MVS_INT_MASK, tmp); in mvs_64xx_init()
423 u32 tmp; in mvs_64xx_interrupt_enable() local
425 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_interrupt_enable()
426 mw32(MVS_GBL_CTL, tmp | INT_EN); in mvs_64xx_interrupt_enable()
432 u32 tmp; in mvs_64xx_interrupt_disable() local
434 tmp = mr32(MVS_GBL_CTL); in mvs_64xx_interrupt_disable()
435 mw32(MVS_GBL_CTL, tmp & ~INT_EN); in mvs_64xx_interrupt_disable()
469 u32 tmp; in mvs_64xx_command_active() local
473 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3)); in mvs_64xx_command_active()
474 } while (tmp & 1 << (slot_idx % 32)); in mvs_64xx_command_active()
476 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3)); in mvs_64xx_command_active()
477 } while (tmp & 1 << (slot_idx % 32)); in mvs_64xx_command_active()
484 u32 tmp; in mvs_64xx_issue_stop() local
487 tmp = mr32(MVS_INT_STAT_SRS_0) | (1U << tfs); in mvs_64xx_issue_stop()
488 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_issue_stop()
491 tmp = mr32(MVS_PCS) | 0xFF00; in mvs_64xx_issue_stop()
492 mw32(MVS_PCS, tmp); in mvs_64xx_issue_stop()
498 u32 tmp, offs; in mvs_64xx_free_reg_set() local
505 tmp = mr32(MVS_PCS); in mvs_64xx_free_reg_set()
506 mw32(MVS_PCS, tmp & ~offs); in mvs_64xx_free_reg_set()
508 tmp = mr32(MVS_CTL); in mvs_64xx_free_reg_set()
509 mw32(MVS_CTL, tmp & ~offs); in mvs_64xx_free_reg_set()
512 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << *tfs); in mvs_64xx_free_reg_set()
513 if (tmp) in mvs_64xx_free_reg_set()
514 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_free_reg_set()
523 u32 tmp, offs; in mvs_64xx_assign_reg_set() local
529 tmp = mr32(MVS_PCS); in mvs_64xx_assign_reg_set()
533 tmp = mr32(MVS_CTL); in mvs_64xx_assign_reg_set()
535 if (!(tmp & offs)) { in mvs_64xx_assign_reg_set()
539 mw32(MVS_PCS, tmp | offs); in mvs_64xx_assign_reg_set()
541 mw32(MVS_CTL, tmp | offs); in mvs_64xx_assign_reg_set()
542 tmp = mr32(MVS_INT_STAT_SRS_0) & (1U << i); in mvs_64xx_assign_reg_set()
543 if (tmp) in mvs_64xx_assign_reg_set()
544 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_assign_reg_set()
608 u32 tmp; in mvs_64xx_phy_work_around() local
611 tmp = mvs_read_port_vsr_data(mvi, i); in mvs_64xx_phy_work_around()
615 tmp &= ~PHY_MODE6_LATECLK; in mvs_64xx_phy_work_around()
617 tmp |= PHY_MODE6_LATECLK; in mvs_64xx_phy_work_around()
618 mvs_write_port_vsr_data(mvi, i, tmp); in mvs_64xx_phy_work_around()
625 u32 tmp; in mvs_64xx_phy_set_link_rate() local
627 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_set_link_rate()
632 tmp &= ~(0xf << 8); in mvs_64xx_phy_set_link_rate()
633 tmp |= lrmin; in mvs_64xx_phy_set_link_rate()
636 tmp &= ~(0xf << 12); in mvs_64xx_phy_set_link_rate()
637 tmp |= lrmax; in mvs_64xx_phy_set_link_rate()
639 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_64xx_phy_set_link_rate()
645 u32 tmp; in mvs_64xx_clear_active_cmds() local
647 tmp = mr32(MVS_PCS); in mvs_64xx_clear_active_cmds()
648 mw32(MVS_PCS, tmp & 0xFFFF); in mvs_64xx_clear_active_cmds()
649 mw32(MVS_PCS, tmp); in mvs_64xx_clear_active_cmds()
650 tmp = mr32(MVS_CTL); in mvs_64xx_clear_active_cmds()
651 mw32(MVS_CTL, tmp & 0xFFFF); in mvs_64xx_clear_active_cmds()
652 mw32(MVS_CTL, tmp); in mvs_64xx_clear_active_cmds()
742 u32 tmp = 0; in mvs_64xx_tune_interrupt() local
756 tmp = 0x10000 | time; in mvs_64xx_tune_interrupt()
757 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_64xx_tune_interrupt()