317 		writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/  in arcmsr_remap_pciregion()
330 		writel(0, &acb->pmuF->host_int_status); /* clear interrupt */  in arcmsr_remap_pciregion()
479 			writel(0, &phbcmu->host_int_status); /*clear interrupt*/  in arcmsr_hbaE_wait_msgint_ready()
625 	reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);  in arcmsr_hbaD_assign_regAddr()
1178 		writel(0, &acb->pmuE->host_int_status);  in arcmsr_resume()
1185 		writel(0, &acb->pmuF->host_int_status);  in arcmsr_resume()
1521 …while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOuts…  in arcmsr_done4abort_postqueue()
2437 		writel(0, &reg->host_int_status); /* clear interrupt */  in arcmsr_hbaE_doorbell_isr()
2694 	writel(0, &reg->host_int_status);  in arcmsr_hbaE_message_isr()
2760 	host_interrupt_status = readl(&phbcmu->host_int_status) &  in arcmsr_hbaC_handle_isr()
2771 		host_interrupt_status = readl(&phbcmu->host_int_status);  in arcmsr_hbaC_handle_isr()
2782 	host_interrupt_status = readl(pmu->host_int_status) &  in arcmsr_hbaD_handle_isr()
2795 		host_interrupt_status = readl(pmu->host_int_status);  in arcmsr_hbaD_handle_isr()
2807 	host_interrupt_status = readl(&pmu->host_int_status) &  in arcmsr_hbaE_handle_isr()
2821 		host_interrupt_status = readl(&pmu->host_int_status);  in arcmsr_hbaE_handle_isr()
2832 	host_interrupt_status = readl(&phbcmu->host_int_status) &  in arcmsr_hbaF_handle_isr()
2846 		host_interrupt_status = readl(&phbcmu->host_int_status);  in arcmsr_hbaF_handle_isr()
3632 		if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {  in arcmsr_hbaC_polling_ccbdone()
4392 		writel(0, &reg->host_int_status); /*clear interrupt*/  in arcmsr_clear_doorbell_queue_buffer()
4400 				writel(0, &reg->host_int_status); /*clear interrupt*/  in arcmsr_clear_doorbell_queue_buffer()