Lines Matching refs:DSR
55 #define DSR 0x14 /* Status Reg */ macro
275 di_write_busy_wait(imxdi, DSR_CAF, DSR); in di_handle_valid_state()
325 di_write_busy_wait(imxdi, DSR_NVF, DSR); in di_handle_invalid_state()
327 di_write_busy_wait(imxdi, DSR_TCO, DSR); in di_handle_invalid_state()
334 return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR)); in di_handle_invalid_state()
377 DSR_MCO | DSR_TCO), DSR); in di_handle_invalid_and_failure_state()
379 dsr = readl(imxdi->ioaddr + DSR); in di_handle_invalid_and_failure_state()
391 di_write_busy_wait(imxdi, DSR_SVF, DSR); in di_handle_invalid_and_failure_state()
394 dsr = readl(imxdi->ioaddr + DSR); in di_handle_invalid_and_failure_state()
415 dsr = readl(imxdi->ioaddr + DSR); in di_handle_state()
479 writel(DSR_WEF, imxdi->ioaddr + DSR); in clear_write_error()
483 if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0) in clear_write_error()
562 dsr = readl(imxdi->ioaddr + DSR); in dryice_rtc_set_time()
621 alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0; in dryice_rtc_read_alarm()
667 dsr = readl(imxdi->ioaddr + DSR); in dryice_irq()
733 di_write_wait(imxdi, DSR_CAF, DSR); in dryice_work()