Lines Matching refs:wcss
154 static int q6v5_wcss_reset(struct q6v5_wcss *wcss) in q6v5_wcss_reset() argument
161 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
163 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
166 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
168 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_reset()
171 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_reset()
175 dev_err(wcss->dev, in q6v5_wcss_reset()
180 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
182 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
187 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
190 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
192 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
196 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
199 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
202 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
208 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_reset()
212 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
214 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
218 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_reset()
221 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
223 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
226 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
228 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_reset()
231 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
233 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_reset()
240 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_start() local
243 qcom_q6v5_prepare(&wcss->q6v5); in q6v5_wcss_start()
246 ret = reset_control_deassert(wcss->wcss_reset); in q6v5_wcss_start()
248 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_wcss_start()
252 ret = reset_control_deassert(wcss->wcss_q6_reset); in q6v5_wcss_start()
254 dev_err(wcss->dev, "wcss_q6_reset failed\n"); in q6v5_wcss_start()
259 ret = regmap_update_bits(wcss->halt_map, in q6v5_wcss_start()
260 wcss->halt_nc + TCSR_GLOBAL_CFG0, in q6v5_wcss_start()
266 ret = regmap_update_bits(wcss->halt_map, in q6v5_wcss_start()
267 wcss->halt_nc + TCSR_GLOBAL_CFG1, in q6v5_wcss_start()
273 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_wcss_start()
275 ret = q6v5_wcss_reset(wcss); in q6v5_wcss_start()
279 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); in q6v5_wcss_start()
281 dev_err(wcss->dev, "start timed out\n"); in q6v5_wcss_start()
286 reset_control_assert(wcss->wcss_q6_reset); in q6v5_wcss_start()
289 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_start()
294 static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss) in q6v5_wcss_qcs404_power_on() argument
300 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_qcs404_power_on()
302 reset_control_deassert(wcss->wcss_reset); in q6v5_wcss_qcs404_power_on()
306 ret = clk_prepare_enable(wcss->gcc_abhs_cbcr); in q6v5_wcss_qcs404_power_on()
311 reset_control_deassert(wcss->wcss_q6_bcr_reset); in q6v5_wcss_qcs404_power_on()
314 ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_qcs404_power_on()
319 ret = clk_prepare_enable(wcss->lcc_csr_cbcr); in q6v5_wcss_qcs404_power_on()
324 ret = clk_prepare_enable(wcss->ahbs_cbcr); in q6v5_wcss_qcs404_power_on()
329 ret = clk_prepare_enable(wcss->tcm_slave_cbcr); in q6v5_wcss_qcs404_power_on()
334 ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_qcs404_power_on()
339 ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_qcs404_power_on()
344 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
346 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
348 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, in q6v5_wcss_qcs404_power_on()
352 dev_err(wcss->dev, in q6v5_wcss_qcs404_power_on()
357 writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE); in q6v5_wcss_qcs404_power_on()
360 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
362 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
365 ret = clk_prepare_enable(wcss->gcc_axim_cbcr); in q6v5_wcss_qcs404_power_on()
370 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
372 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
375 writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
377 writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
379 writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
381 writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
388 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) | in q6v5_wcss_qcs404_power_on()
389 (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_wcss_qcs404_power_on()
392 writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
393 writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_wcss_qcs404_power_on()
395 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
397 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_power_on()
400 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
402 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
405 ret = clk_prepare_enable(wcss->lcc_bcr_sleep); in q6v5_wcss_qcs404_power_on()
412 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
414 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_wcss_qcs404_power_on()
415 clk_disable_unprepare(wcss->gcc_axim_cbcr); in q6v5_wcss_qcs404_power_on()
417 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
419 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_wcss_qcs404_power_on()
421 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
423 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_wcss_qcs404_power_on()
424 clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_qcs404_power_on()
426 clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_qcs404_power_on()
428 clk_disable_unprepare(wcss->tcm_slave_cbcr); in q6v5_wcss_qcs404_power_on()
430 clk_disable_unprepare(wcss->ahbs_cbcr); in q6v5_wcss_qcs404_power_on()
432 clk_disable_unprepare(wcss->lcc_csr_cbcr); in q6v5_wcss_qcs404_power_on()
434 clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_qcs404_power_on()
436 clk_disable_unprepare(wcss->gcc_abhs_cbcr); in q6v5_wcss_qcs404_power_on()
441 static inline int q6v5_wcss_qcs404_reset(struct q6v5_wcss *wcss) in q6v5_wcss_qcs404_reset() argument
445 writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC); in q6v5_wcss_qcs404_reset()
448 val = readl(wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_reset()
450 writel(val, wcss->reg_base + Q6SS_RESET_REG); in q6v5_wcss_qcs404_reset()
457 struct q6v5_wcss *wcss = rproc->priv; in q6v5_qcs404_wcss_start() local
460 ret = clk_prepare_enable(wcss->xo); in q6v5_qcs404_wcss_start()
464 ret = regulator_enable(wcss->cx_supply); in q6v5_qcs404_wcss_start()
468 qcom_q6v5_prepare(&wcss->q6v5); in q6v5_qcs404_wcss_start()
470 ret = q6v5_wcss_qcs404_power_on(wcss); in q6v5_qcs404_wcss_start()
472 dev_err(wcss->dev, "wcss clk_enable failed\n"); in q6v5_qcs404_wcss_start()
476 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); in q6v5_qcs404_wcss_start()
478 q6v5_wcss_qcs404_reset(wcss); in q6v5_qcs404_wcss_start()
480 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); in q6v5_qcs404_wcss_start()
482 dev_err(wcss->dev, "start timed out\n"); in q6v5_qcs404_wcss_start()
489 regulator_disable(wcss->cx_supply); in q6v5_qcs404_wcss_start()
491 clk_disable_unprepare(wcss->xo); in q6v5_qcs404_wcss_start()
496 static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss, in q6v5_wcss_halt_axi_port() argument
524 dev_err(wcss->dev, "port failed halt\n"); in q6v5_wcss_halt_axi_port()
530 static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss *wcss) in q6v5_qcs404_wcss_shutdown() argument
535 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); in q6v5_qcs404_wcss_shutdown()
538 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
540 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
543 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) & in q6v5_qcs404_wcss_shutdown()
545 wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_qcs404_wcss_shutdown()
548 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
550 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_qcs404_wcss_shutdown()
552 clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); in q6v5_qcs404_wcss_shutdown()
553 clk_disable_unprepare(wcss->lcc_csr_cbcr); in q6v5_qcs404_wcss_shutdown()
554 clk_disable_unprepare(wcss->tcm_slave_cbcr); in q6v5_qcs404_wcss_shutdown()
555 clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); in q6v5_qcs404_wcss_shutdown()
556 clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); in q6v5_qcs404_wcss_shutdown()
558 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_qcs404_wcss_shutdown()
560 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); in q6v5_qcs404_wcss_shutdown()
562 val = readl(wcss->reg_base + Q6SS_XO_CBCR); in q6v5_qcs404_wcss_shutdown()
564 writel(val, wcss->reg_base + Q6SS_XO_CBCR); in q6v5_qcs404_wcss_shutdown()
566 clk_disable_unprepare(wcss->ahbs_cbcr); in q6v5_qcs404_wcss_shutdown()
567 clk_disable_unprepare(wcss->lcc_bcr_sleep); in q6v5_qcs404_wcss_shutdown()
569 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
571 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_qcs404_wcss_shutdown()
573 clk_disable_unprepare(wcss->gcc_abhs_cbcr); in q6v5_qcs404_wcss_shutdown()
575 ret = reset_control_assert(wcss->wcss_reset); in q6v5_qcs404_wcss_shutdown()
577 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_qcs404_wcss_shutdown()
582 ret = reset_control_deassert(wcss->wcss_reset); in q6v5_qcs404_wcss_shutdown()
584 dev_err(wcss->dev, "wcss_reset failed\n"); in q6v5_qcs404_wcss_shutdown()
589 clk_disable_unprepare(wcss->gcc_axim_cbcr); in q6v5_qcs404_wcss_shutdown()
594 static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss) in q6v5_wcss_powerdown() argument
600 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); in q6v5_wcss_powerdown()
603 val = readl(wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
605 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
610 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
614 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
617 ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS, in q6v5_wcss_powerdown()
621 dev_err(wcss->dev, in q6v5_wcss_powerdown()
627 reset_control_assert(wcss->wcss_aon_reset); in q6v5_wcss_powerdown()
630 val = readl(wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
632 writel(val, wcss->rmb_base + SSCAON_CONFIG); in q6v5_wcss_powerdown()
635 reset_control_assert(wcss->wcss_reset); in q6v5_wcss_powerdown()
640 static int q6v5_q6_powerdown(struct q6v5_wcss *wcss) in q6v5_q6_powerdown() argument
647 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6); in q6v5_q6_powerdown()
650 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
652 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); in q6v5_q6_powerdown()
655 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
657 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
661 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
665 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
669 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
673 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
675 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); in q6v5_q6_powerdown()
680 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
682 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
686 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); in q6v5_q6_powerdown()
690 ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS, in q6v5_q6_powerdown()
694 dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret); in q6v5_q6_powerdown()
699 reset_control_assert(wcss->wcss_reset); in q6v5_q6_powerdown()
702 reset_control_assert(wcss->wcss_q6_reset); in q6v5_q6_powerdown()
709 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_stop() local
713 if (wcss->requires_force_stop) { in q6v5_wcss_stop()
714 ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); in q6v5_wcss_stop()
716 dev_err(wcss->dev, "timed out on wait\n"); in q6v5_wcss_stop()
721 if (wcss->version == WCSS_QCS404) { in q6v5_wcss_stop()
722 ret = q6v5_qcs404_wcss_shutdown(wcss); in q6v5_wcss_stop()
726 ret = q6v5_wcss_powerdown(wcss); in q6v5_wcss_stop()
731 ret = q6v5_q6_powerdown(wcss); in q6v5_wcss_stop()
736 qcom_q6v5_unprepare(&wcss->q6v5); in q6v5_wcss_stop()
743 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_da_to_va() local
746 offset = da - wcss->mem_reloc; in q6v5_wcss_da_to_va()
747 if (offset < 0 || offset + len > wcss->mem_size) in q6v5_wcss_da_to_va()
750 return wcss->mem_region + offset; in q6v5_wcss_da_to_va()
755 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_load() local
758 ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, in q6v5_wcss_load()
759 0, wcss->mem_region, wcss->mem_phys, in q6v5_wcss_load()
760 wcss->mem_size, &wcss->mem_reloc); in q6v5_wcss_load()
764 qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size); in q6v5_wcss_load()
786 static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, in q6v5_wcss_init_reset() argument
789 struct device *dev = wcss->dev; in q6v5_wcss_init_reset()
792 wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset"); in q6v5_wcss_init_reset()
793 if (IS_ERR(wcss->wcss_aon_reset)) { in q6v5_wcss_init_reset()
794 dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); in q6v5_wcss_init_reset()
795 return PTR_ERR(wcss->wcss_aon_reset); in q6v5_wcss_init_reset()
799 wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset"); in q6v5_wcss_init_reset()
800 if (IS_ERR(wcss->wcss_reset)) { in q6v5_wcss_init_reset()
801 dev_err(wcss->dev, "unable to acquire wcss_reset\n"); in q6v5_wcss_init_reset()
802 return PTR_ERR(wcss->wcss_reset); in q6v5_wcss_init_reset()
806 wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset"); in q6v5_wcss_init_reset()
807 if (IS_ERR(wcss->wcss_q6_reset)) { in q6v5_wcss_init_reset()
808 dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); in q6v5_wcss_init_reset()
809 return PTR_ERR(wcss->wcss_q6_reset); in q6v5_wcss_init_reset()
813 wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset"); in q6v5_wcss_init_reset()
814 if (IS_ERR(wcss->wcss_q6_bcr_reset)) { in q6v5_wcss_init_reset()
815 dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n"); in q6v5_wcss_init_reset()
816 return PTR_ERR(wcss->wcss_q6_bcr_reset); in q6v5_wcss_init_reset()
822 static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, in q6v5_wcss_init_mmio() argument
834 wcss->reg_base = devm_ioremap(&pdev->dev, res->start, in q6v5_wcss_init_mmio()
836 if (!wcss->reg_base) in q6v5_wcss_init_mmio()
839 if (wcss->version == WCSS_IPQ8074) { in q6v5_wcss_init_mmio()
841 wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res); in q6v5_wcss_init_mmio()
842 if (IS_ERR(wcss->rmb_base)) in q6v5_wcss_init_mmio()
843 return PTR_ERR(wcss->rmb_base); in q6v5_wcss_init_mmio()
853 wcss->halt_map = syscon_node_to_regmap(syscon); in q6v5_wcss_init_mmio()
855 if (IS_ERR(wcss->halt_map)) in q6v5_wcss_init_mmio()
856 return PTR_ERR(wcss->halt_map); in q6v5_wcss_init_mmio()
867 wcss->halt_q6 = halt_reg[0]; in q6v5_wcss_init_mmio()
868 wcss->halt_wcss = halt_reg[1]; in q6v5_wcss_init_mmio()
869 wcss->halt_nc = halt_reg[2]; in q6v5_wcss_init_mmio()
874 static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) in q6v5_alloc_memory_region() argument
878 struct device *dev = wcss->dev; in q6v5_alloc_memory_region()
890 wcss->mem_phys = rmem->base; in q6v5_alloc_memory_region()
891 wcss->mem_reloc = rmem->base; in q6v5_alloc_memory_region()
892 wcss->mem_size = rmem->size; in q6v5_alloc_memory_region()
893 wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); in q6v5_alloc_memory_region()
894 if (!wcss->mem_region) { in q6v5_alloc_memory_region()
903 static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) in q6v5_wcss_init_clock() argument
907 wcss->xo = devm_clk_get(wcss->dev, "xo"); in q6v5_wcss_init_clock()
908 if (IS_ERR(wcss->xo)) { in q6v5_wcss_init_clock()
909 ret = PTR_ERR(wcss->xo); in q6v5_wcss_init_clock()
911 dev_err(wcss->dev, "failed to get xo clock"); in q6v5_wcss_init_clock()
915 wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr"); in q6v5_wcss_init_clock()
916 if (IS_ERR(wcss->gcc_abhs_cbcr)) { in q6v5_wcss_init_clock()
917 ret = PTR_ERR(wcss->gcc_abhs_cbcr); in q6v5_wcss_init_clock()
919 dev_err(wcss->dev, "failed to get gcc abhs clock"); in q6v5_wcss_init_clock()
923 wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr"); in q6v5_wcss_init_clock()
924 if (IS_ERR(wcss->gcc_axim_cbcr)) { in q6v5_wcss_init_clock()
925 ret = PTR_ERR(wcss->gcc_axim_cbcr); in q6v5_wcss_init_clock()
927 dev_err(wcss->dev, "failed to get gcc axim clock\n"); in q6v5_wcss_init_clock()
931 wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
933 if (IS_ERR(wcss->ahbfabric_cbcr_clk)) { in q6v5_wcss_init_clock()
934 ret = PTR_ERR(wcss->ahbfabric_cbcr_clk); in q6v5_wcss_init_clock()
936 dev_err(wcss->dev, "failed to get ahbfabric clock\n"); in q6v5_wcss_init_clock()
940 wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc"); in q6v5_wcss_init_clock()
941 if (IS_ERR(wcss->lcc_csr_cbcr)) { in q6v5_wcss_init_clock()
942 ret = PTR_ERR(wcss->lcc_csr_cbcr); in q6v5_wcss_init_clock()
944 dev_err(wcss->dev, "failed to get csr cbcr clk\n"); in q6v5_wcss_init_clock()
948 wcss->ahbs_cbcr = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
950 if (IS_ERR(wcss->ahbs_cbcr)) { in q6v5_wcss_init_clock()
951 ret = PTR_ERR(wcss->ahbs_cbcr); in q6v5_wcss_init_clock()
953 dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n"); in q6v5_wcss_init_clock()
957 wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev, in q6v5_wcss_init_clock()
959 if (IS_ERR(wcss->tcm_slave_cbcr)) { in q6v5_wcss_init_clock()
960 ret = PTR_ERR(wcss->tcm_slave_cbcr); in q6v5_wcss_init_clock()
962 dev_err(wcss->dev, "failed to get tcm cbcr clk\n"); in q6v5_wcss_init_clock()
966 wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc"); in q6v5_wcss_init_clock()
967 if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) { in q6v5_wcss_init_clock()
968 ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr); in q6v5_wcss_init_clock()
970 dev_err(wcss->dev, "failed to get abhm cbcr clk\n"); in q6v5_wcss_init_clock()
974 wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc"); in q6v5_wcss_init_clock()
975 if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) { in q6v5_wcss_init_clock()
976 ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr); in q6v5_wcss_init_clock()
978 dev_err(wcss->dev, "failed to get axim cbcr clk\n"); in q6v5_wcss_init_clock()
982 wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep"); in q6v5_wcss_init_clock()
983 if (IS_ERR(wcss->lcc_bcr_sleep)) { in q6v5_wcss_init_clock()
984 ret = PTR_ERR(wcss->lcc_bcr_sleep); in q6v5_wcss_init_clock()
986 dev_err(wcss->dev, "failed to get bcr cbcr clk\n"); in q6v5_wcss_init_clock()
993 static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) in q6v5_wcss_init_regulator() argument
995 wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); in q6v5_wcss_init_regulator()
996 if (IS_ERR(wcss->cx_supply)) in q6v5_wcss_init_regulator()
997 return PTR_ERR(wcss->cx_supply); in q6v5_wcss_init_regulator()
999 regulator_set_load(wcss->cx_supply, 100000); in q6v5_wcss_init_regulator()
1007 struct q6v5_wcss *wcss; in q6v5_wcss_probe() local
1016 desc->firmware_name, sizeof(*wcss)); in q6v5_wcss_probe()
1022 wcss = rproc->priv; in q6v5_wcss_probe()
1023 wcss->dev = &pdev->dev; in q6v5_wcss_probe()
1024 wcss->version = desc->version; in q6v5_wcss_probe()
1026 wcss->version = desc->version; in q6v5_wcss_probe()
1027 wcss->requires_force_stop = desc->requires_force_stop; in q6v5_wcss_probe()
1029 ret = q6v5_wcss_init_mmio(wcss, pdev); in q6v5_wcss_probe()
1033 ret = q6v5_alloc_memory_region(wcss); in q6v5_wcss_probe()
1037 if (wcss->version == WCSS_QCS404) { in q6v5_wcss_probe()
1038 ret = q6v5_wcss_init_clock(wcss); in q6v5_wcss_probe()
1042 ret = q6v5_wcss_init_regulator(wcss); in q6v5_wcss_probe()
1047 ret = q6v5_wcss_init_reset(wcss, desc); in q6v5_wcss_probe()
1051 ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL); in q6v5_wcss_probe()
1055 qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss"); in q6v5_wcss_probe()
1056 qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); in q6v5_wcss_probe()
1059 wcss->sysmon = qcom_add_sysmon_subdev(rproc, in q6v5_wcss_probe()
1080 struct q6v5_wcss *wcss = rproc->priv; in q6v5_wcss_remove() local
1082 qcom_q6v5_deinit(&wcss->q6v5); in q6v5_wcss_remove()