21 	pc = &config_store.mode_set[src][idx].power_control;  in amd_pmf_set_cnqf()
203 	ms->power_control.fppt = out.ps[APMF_CNQF_QUIET].fppt;  in amd_pmf_update_mode_set()
204 	ms->power_control.sppt = out.ps[APMF_CNQF_QUIET].sppt;  in amd_pmf_update_mode_set()
205 	ms->power_control.sppt_apu_only = out.ps[APMF_CNQF_QUIET].sppt_apu_only;  in amd_pmf_update_mode_set()
206 	ms->power_control.spl = out.ps[APMF_CNQF_QUIET].spl;  in amd_pmf_update_mode_set()
207 	ms->power_control.stt_min = out.ps[APMF_CNQF_QUIET].stt_min_limit;  in amd_pmf_update_mode_set()
208 	ms->power_control.stt_skin_temp[STT_TEMP_APU] =  in amd_pmf_update_mode_set()
210 	ms->power_control.stt_skin_temp[STT_TEMP_HS2] =  in amd_pmf_update_mode_set()
217 	ms->power_control.fppt = out.ps[APMF_CNQF_BALANCE].fppt;  in amd_pmf_update_mode_set()
218 	ms->power_control.sppt = out.ps[APMF_CNQF_BALANCE].sppt;  in amd_pmf_update_mode_set()
219 	ms->power_control.sppt_apu_only = out.ps[APMF_CNQF_BALANCE].sppt_apu_only;  in amd_pmf_update_mode_set()
220 	ms->power_control.spl = out.ps[APMF_CNQF_BALANCE].spl;  in amd_pmf_update_mode_set()
221 	ms->power_control.stt_min = out.ps[APMF_CNQF_BALANCE].stt_min_limit;  in amd_pmf_update_mode_set()
222 	ms->power_control.stt_skin_temp[STT_TEMP_APU] =  in amd_pmf_update_mode_set()
224 	ms->power_control.stt_skin_temp[STT_TEMP_HS2] =  in amd_pmf_update_mode_set()
231 	ms->power_control.fppt = out.ps[APMF_CNQF_PERFORMANCE].fppt;  in amd_pmf_update_mode_set()
232 	ms->power_control.sppt = out.ps[APMF_CNQF_PERFORMANCE].sppt;  in amd_pmf_update_mode_set()
233 	ms->power_control.sppt_apu_only = out.ps[APMF_CNQF_PERFORMANCE].sppt_apu_only;  in amd_pmf_update_mode_set()
234 	ms->power_control.spl = out.ps[APMF_CNQF_PERFORMANCE].spl;  in amd_pmf_update_mode_set()
235 	ms->power_control.stt_min = out.ps[APMF_CNQF_PERFORMANCE].stt_min_limit;  in amd_pmf_update_mode_set()
236 	ms->power_control.stt_skin_temp[STT_TEMP_APU] =  in amd_pmf_update_mode_set()
238 	ms->power_control.stt_skin_temp[STT_TEMP_HS2] =  in amd_pmf_update_mode_set()
245 	ms->power_control.fppt = out.ps[APMF_CNQF_TURBO].fppt;  in amd_pmf_update_mode_set()
246 	ms->power_control.sppt = out.ps[APMF_CNQF_TURBO].sppt;  in amd_pmf_update_mode_set()
247 	ms->power_control.sppt_apu_only = out.ps[APMF_CNQF_TURBO].sppt_apu_only;  in amd_pmf_update_mode_set()
248 	ms->power_control.spl = out.ps[APMF_CNQF_TURBO].spl;  in amd_pmf_update_mode_set()
249 	ms->power_control.stt_min = out.ps[APMF_CNQF_TURBO].stt_min_limit;  in amd_pmf_update_mode_set()
250 	ms->power_control.stt_skin_temp[STT_TEMP_APU] =  in amd_pmf_update_mode_set()
252 	ms->power_control.stt_skin_temp[STT_TEMP_HS2] =  in amd_pmf_update_mode_set()