Lines Matching refs:g
85 const struct msm_pingroup *g) \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
90 const struct msm_pingroup *g) \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
102 const struct msm_pingroup *g) in MSM_ACCESSOR()
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
106 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
189 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
194 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
195 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
197 for (i = 0; i < g->nfuncs; i++) { in msm_pinmux_set_mux()
198 if (g->funcs[i] == function) in msm_pinmux_set_mux()
202 if (WARN_ON(i == g->nfuncs)) in msm_pinmux_set_mux()
221 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
229 if (i == gpio_func && (val & BIT(g->oe_bit)) && in msm_pinmux_set_mux()
231 u32 io_val = msm_readl_io(pctrl, g); in msm_pinmux_set_mux()
233 if (io_val & BIT(g->in_bit)) { in msm_pinmux_set_mux()
234 if (!(io_val & BIT(g->out_bit))) in msm_pinmux_set_mux()
235 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
237 if (io_val & BIT(g->out_bit)) in msm_pinmux_set_mux()
238 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); in msm_pinmux_set_mux()
243 if (val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
244 val &= ~BIT(g->egpio_enable); in msm_pinmux_set_mux()
247 val |= i << g->mux_bit; in msm_pinmux_set_mux()
249 if (egpio_func && val & BIT(g->egpio_present)) in msm_pinmux_set_mux()
250 val |= BIT(g->egpio_enable); in msm_pinmux_set_mux()
253 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
266 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
279 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio() local
282 if (!g->nfuncs) in msm_pinmux_request_gpio()
285 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
298 const struct msm_pingroup *g, in msm_config_reg() argument
308 *bit = g->pull_bit; in msm_config_reg()
312 *bit = g->od_bit; in msm_config_reg()
316 *bit = g->drv_bit; in msm_config_reg()
321 *bit = g->oe_bit; in msm_config_reg()
346 const struct msm_pingroup *g; in msm_config_group_get() local
355 g = &pctrl->soc->groups[group]; in msm_config_group_get()
357 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
361 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
406 val = msm_readl_io(pctrl, g); in msm_config_group_get()
407 arg = !!(val & BIT(g->in_bit)); in msm_config_group_get()
429 const struct msm_pingroup *g; in msm_config_group_set() local
440 g = &pctrl->soc->groups[group]; in msm_config_group_set()
446 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
483 val = msm_readl_io(pctrl, g); in msm_config_group_set()
485 val |= BIT(g->out_bit); in msm_config_group_set()
487 val &= ~BIT(g->out_bit); in msm_config_group_set()
488 msm_writel_io(val, pctrl, g); in msm_config_group_set()
511 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
514 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
529 const struct msm_pingroup *g; in msm_gpio_direction_input() local
534 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
538 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
539 val &= ~BIT(g->oe_bit); in msm_gpio_direction_input()
540 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
549 const struct msm_pingroup *g; in msm_gpio_direction_output() local
554 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
558 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
560 val |= BIT(g->out_bit); in msm_gpio_direction_output()
562 val &= ~BIT(g->out_bit); in msm_gpio_direction_output()
563 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
565 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
566 val |= BIT(g->oe_bit); in msm_gpio_direction_output()
567 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
577 const struct msm_pingroup *g; in msm_gpio_get_direction() local
580 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
582 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
584 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : in msm_gpio_get_direction()
590 const struct msm_pingroup *g; in msm_gpio_get() local
594 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
596 val = msm_readl_io(pctrl, g); in msm_gpio_get()
597 return !!(val & BIT(g->in_bit)); in msm_gpio_get()
602 const struct msm_pingroup *g; in msm_gpio_set() local
607 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
611 val = msm_readl_io(pctrl, g); in msm_gpio_set()
613 val |= BIT(g->out_bit); in msm_gpio_set()
615 val &= ~BIT(g->out_bit); in msm_gpio_set()
616 msm_writel_io(val, pctrl, g); in msm_gpio_set()
630 const struct msm_pingroup *g; in msm_gpio_dbg_show_one() local
656 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
657 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
658 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
660 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one()
661 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one()
662 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one()
663 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one()
665 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one()
666 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
669 val = !!(io_reg & BIT(g->out_bit)); in msm_gpio_dbg_show_one()
671 val = !!(io_reg & BIT(g->in_bit)); in msm_gpio_dbg_show_one()
674 seq_printf(s, " %-8s: egpio\n", g->name); in msm_gpio_dbg_show_one()
678 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); in msm_gpio_dbg_show_one()
784 const struct msm_pingroup *g, in msm_gpio_update_dual_edge_pos() argument
792 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
794 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
795 pol ^= BIT(g->intr_polarity_bit); in msm_gpio_update_dual_edge_pos()
796 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
798 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
799 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
811 const struct msm_pingroup *g; in msm_gpio_irq_mask() local
821 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
825 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
847 val &= ~BIT(g->intr_raw_status_bit); in msm_gpio_irq_mask()
849 val &= ~BIT(g->intr_enable_bit); in msm_gpio_irq_mask()
850 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
861 const struct msm_pingroup *g; in msm_gpio_irq_unmask() local
871 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
875 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
876 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_unmask()
877 val |= BIT(g->intr_enable_bit); in msm_gpio_irq_unmask()
878 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
926 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent() local
932 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
945 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
963 const struct msm_pingroup *g; in msm_gpio_irq_ack() local
972 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
976 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
979 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
1007 const struct msm_pingroup *g; in msm_gpio_irq_set_type() local
1028 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
1035 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) in msm_gpio_irq_set_type()
1045 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1050 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
1051 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1059 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1060 val &= ~(7 << g->intr_target_bit); in msm_gpio_irq_set_type()
1061 val |= g->intr_target_kpss_val << g->intr_target_bit; in msm_gpio_irq_set_type()
1062 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1070 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1071 was_enabled = val & BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1072 val |= BIT(g->intr_raw_status_bit); in msm_gpio_irq_set_type()
1073 if (g->intr_detection_width == 2) { in msm_gpio_irq_set_type()
1074 val &= ~(3 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1075 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1078 val |= 1 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1079 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1082 val |= 2 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1083 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1086 val |= 3 << g->intr_detection_bit; in msm_gpio_irq_set_type()
1087 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1092 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1095 } else if (g->intr_detection_width == 1) { in msm_gpio_irq_set_type()
1096 val &= ~(1 << g->intr_detection_bit); in msm_gpio_irq_set_type()
1097 val &= ~(1 << g->intr_polarity_bit); in msm_gpio_irq_set_type()
1100 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1101 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1104 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1107 val |= BIT(g->intr_detection_bit); in msm_gpio_irq_set_type()
1108 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1113 val |= BIT(g->intr_polarity_bit); in msm_gpio_irq_set_type()
1119 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1127 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1130 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1228 const struct msm_pingroup *g; in msm_gpio_irq_handler() local
1242 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1243 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1244 if (val & BIT(g->intr_status_bit)) { in msm_gpio_irq_handler()