Lines Matching refs:pin_reg
41 u32 pin_reg; in amd_gpio_get_direction() local
45 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
48 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) in amd_gpio_get_direction()
57 u32 pin_reg; in amd_gpio_direction_input() local
61 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_input()
63 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
72 u32 pin_reg; in amd_gpio_direction_output() local
77 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
78 pin_reg |= BIT(OUTPUT_ENABLE_OFF); in amd_gpio_direction_output()
80 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_direction_output()
83 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
91 u32 pin_reg; in amd_gpio_get_value() local
96 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
99 return !!(pin_reg & BIT(PIN_STS_OFF)); in amd_gpio_get_value()
104 u32 pin_reg; in amd_gpio_set_value() local
109 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
111 pin_reg |= BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); in amd_gpio_set_value()
114 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
122 u32 pin_reg; in amd_gpio_set_debounce() local
128 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; in amd_gpio_set_debounce()
132 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
144 pin_reg |= 1; in amd_gpio_set_debounce()
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
149 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
154 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
159 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
161 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
164 pin_reg |= time & DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
166 pin_reg |= BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
168 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_set_debounce()
172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_set_debounce()
173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); in amd_gpio_set_debounce()
174 pin_reg &= ~DB_TMR_OUT_MASK; in amd_gpio_set_debounce()
175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); in amd_gpio_set_debounce()
177 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
198 u32 pin_reg; in amd_gpio_dbg_show() local
251 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
254 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { in amd_gpio_dbg_show()
255 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & in amd_gpio_dbg_show()
263 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && in amd_gpio_dbg_show()
269 if (pin_reg & BIT(LEVEL_TRIG_OFF)) in amd_gpio_dbg_show()
280 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) in amd_gpio_dbg_show()
290 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) in amd_gpio_dbg_show()
296 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) in amd_gpio_dbg_show()
302 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) in amd_gpio_dbg_show()
308 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { in amd_gpio_dbg_show()
310 if (pin_reg & BIT(PULL_UP_SEL_OFF)) in amd_gpio_dbg_show()
322 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) in amd_gpio_dbg_show()
328 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { in amd_gpio_dbg_show()
330 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) in amd_gpio_dbg_show()
336 if (pin_reg & BIT(PIN_STS_OFF)) in amd_gpio_dbg_show()
343 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; in amd_gpio_dbg_show()
345 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); in amd_gpio_dbg_show()
346 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); in amd_gpio_dbg_show()
347 time = pin_reg & DB_TMR_OUT_MASK; in amd_gpio_dbg_show()
371 seq_printf(s, " 0x%x\n", pin_reg); in amd_gpio_dbg_show()
381 u32 pin_reg; in amd_gpio_irq_enable() local
389 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
390 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_enable()
391 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_enable()
392 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
398 u32 pin_reg; in amd_gpio_irq_disable() local
404 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
405 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); in amd_gpio_irq_disable()
406 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_disable()
407 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
415 u32 pin_reg; in amd_gpio_irq_mask() local
421 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
422 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_mask()
423 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
429 u32 pin_reg; in amd_gpio_irq_unmask() local
435 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
436 pin_reg |= BIT(INTERRUPT_MASK_OFF); in amd_gpio_irq_unmask()
437 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
443 u32 pin_reg; in amd_gpio_irq_set_wake() local
451 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_wake()
454 pin_reg |= wake_mask; in amd_gpio_irq_set_wake()
456 pin_reg &= ~wake_mask; in amd_gpio_irq_set_wake()
458 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_wake()
490 u32 pin_reg, pin_reg_irq_en, mask; in amd_gpio_irq_set_type() local
496 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
500 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
501 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
502 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
507 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
508 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
509 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
514 pin_reg &= ~BIT(LEVEL_TRIG_OFF); in amd_gpio_irq_set_type()
515 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
516 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
521 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
522 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
523 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
528 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; in amd_gpio_irq_set_type()
529 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); in amd_gpio_irq_set_type()
530 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; in amd_gpio_irq_set_type()
542 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; in amd_gpio_irq_set_type()
559 pin_reg_irq_en = pin_reg; in amd_gpio_irq_set_type()
565 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
732 u32 pin_reg; in amd_pinconf_get() local
739 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_get()
743 arg = pin_reg & DB_TMR_OUT_MASK; in amd_pinconf_get()
747 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); in amd_pinconf_get()
751 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); in amd_pinconf_get()
755 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; in amd_pinconf_get()
775 u32 pin_reg; in amd_pinconf_set() local
784 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_set()
788 pin_reg &= ~DB_TMR_OUT_MASK; in amd_pinconf_set()
789 pin_reg |= arg & DB_TMR_OUT_MASK; in amd_pinconf_set()
793 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); in amd_pinconf_set()
794 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; in amd_pinconf_set()
798 pin_reg &= ~BIT(PULL_UP_SEL_OFF); in amd_pinconf_set()
799 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; in amd_pinconf_set()
800 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); in amd_pinconf_set()
801 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; in amd_pinconf_set()
805 pin_reg &= ~(DRV_STRENGTH_SEL_MASK in amd_pinconf_set()
807 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) in amd_pinconf_set()
817 writel(pin_reg, gpio_dev->base + pin*4); in amd_pinconf_set()
871 u32 pin_reg, mask; in amd_gpio_irq_init() local
887 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_irq_init()
888 pin_reg &= ~mask; in amd_gpio_irq_init()
889 writel(pin_reg, gpio_dev->base + i * 4); in amd_gpio_irq_init()