Lines Matching refs:index
284 unsigned int index) in tegra186_usb2_lane_probe() argument
294 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
295 usb2->base.index = index; in tegra186_usb2_lane_probe()
320 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk() local
326 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
328 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
331 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
333 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
342 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
345 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
348 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
350 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
353 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
356 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
359 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
361 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
364 value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index)); in tegra186_utmi_enable_phy_sleepwalk()
385 ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index)); in tegra186_utmi_enable_phy_sleepwalk()
388 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
391 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
396 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index)); in tegra186_utmi_enable_phy_sleepwalk()
398 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index)); in tegra186_utmi_enable_phy_sleepwalk()
429 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index)); in tegra186_utmi_enable_phy_sleepwalk()
432 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
434 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
439 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
442 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
445 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
448 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
451 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
453 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
464 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk() local
470 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_disable_phy_sleepwalk()
472 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_disable_phy_sleepwalk()
475 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_disable_phy_sleepwalk()
478 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_disable_phy_sleepwalk()
481 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_disable_phy_sleepwalk()
484 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_disable_phy_sleepwalk()
487 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_disable_phy_sleepwalk()
489 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index)); in tegra186_utmi_disable_phy_sleepwalk()
492 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index)); in tegra186_utmi_disable_phy_sleepwalk()
494 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index)); in tegra186_utmi_disable_phy_sleepwalk()
504 unsigned int index = lane->index; in tegra186_utmi_enable_phy_wake() local
511 value |= USB2_PORT_WAKEUP_EVENT(index); in tegra186_utmi_enable_phy_wake()
518 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index); in tegra186_utmi_enable_phy_wake()
529 unsigned int index = lane->index; in tegra186_utmi_disable_phy_wake() local
536 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index); in tegra186_utmi_disable_phy_wake()
543 value |= USB2_PORT_WAKEUP_EVENT(index); in tegra186_utmi_disable_phy_wake()
554 unsigned int index = lane->index; in tegra186_utmi_phy_remote_wake_detected() local
558 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) && in tegra186_utmi_phy_remote_wake_detected()
559 (value & USB2_PORT_WAKEUP_EVENT(index))) in tegra186_utmi_phy_remote_wake_detected()
647 unsigned int index = lane->index; in tegra186_utmi_pad_power_on() local
653 port = tegra_xusb_find_usb2_port(padctl, index); in tegra186_utmi_pad_power_on()
655 dev_err(dev, "no port found for USB2 lane %u\n", index); in tegra186_utmi_pad_power_on()
659 dev_dbg(dev, "power on UTMI pad %u\n", index); in tegra186_utmi_pad_power_on()
665 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra186_utmi_pad_power_on()
667 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra186_utmi_pad_power_on()
669 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra186_utmi_pad_power_on()
671 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra186_utmi_pad_power_on()
678 unsigned int index = lane->index; in tegra186_utmi_pad_power_down() local
684 dev_dbg(padctl->dev, "power down UTMI pad %u\n", index); in tegra186_utmi_pad_power_down()
686 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra186_utmi_pad_power_down()
688 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra186_utmi_pad_power_down()
690 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra186_utmi_pad_power_down()
692 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra186_utmi_pad_power_down()
757 lane->index); in tegra186_utmi_phy_set_mode()
797 unsigned int index = lane->index; in tegra186_utmi_phy_power_on() local
801 port = tegra_xusb_find_usb2_port(padctl, index); in tegra186_utmi_phy_power_on()
803 dev_err(dev, "no port found for USB2 lane %u\n", index); in tegra186_utmi_phy_power_on()
808 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index)); in tegra186_utmi_phy_power_on()
809 value |= (PORT_XUSB << USB2_PORT_SHIFT(index)); in tegra186_utmi_phy_power_on()
813 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index)); in tegra186_utmi_phy_power_on()
816 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index)); in tegra186_utmi_phy_power_on()
818 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index)); in tegra186_utmi_phy_power_on()
820 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index)); in tegra186_utmi_phy_power_on()
822 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index)); in tegra186_utmi_phy_power_on()
826 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra186_utmi_phy_power_on()
834 hs_current_level = (int)priv->calib.hs_curr_level[index] + in tegra186_utmi_phy_power_on()
844 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]); in tegra186_utmi_phy_power_on()
847 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra186_utmi_phy_power_on()
849 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra186_utmi_phy_power_on()
854 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra186_utmi_phy_power_on()
873 unsigned int index = lane->index; in tegra186_utmi_phy_init() local
877 port = tegra_xusb_find_usb2_port(padctl, index); in tegra186_utmi_phy_init()
879 dev_err(dev, "no port found for USB2 lane %u\n", index); in tegra186_utmi_phy_init()
887 index, err); in tegra186_utmi_phy_init()
900 unsigned int index = lane->index; in tegra186_utmi_phy_exit() local
904 port = tegra_xusb_find_usb2_port(padctl, index); in tegra186_utmi_phy_exit()
906 dev_err(dev, "no port found for USB2 lane %u\n", index); in tegra186_utmi_phy_exit()
914 index, err); in tegra186_utmi_phy_exit()
1004 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); in tegra186_usb2_port_map()
1018 unsigned int index) in tegra186_usb3_lane_probe() argument
1028 usb3->base.soc = &pad->soc->lanes[index]; in tegra186_usb3_lane_probe()
1029 usb3->base.index = index; in tegra186_usb3_lane_probe()
1053 unsigned int index = lane->index; in tegra186_usb3_enable_phy_sleepwalk() local
1059 value |= SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra186_usb3_enable_phy_sleepwalk()
1065 value |= SSPX_ELPG_CLAMP_EN(index); in tegra186_usb3_enable_phy_sleepwalk()
1078 unsigned int index = lane->index; in tegra186_usb3_disable_phy_sleepwalk() local
1084 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra186_usb3_disable_phy_sleepwalk()
1090 value &= ~SSPX_ELPG_CLAMP_EN(index); in tegra186_usb3_disable_phy_sleepwalk()
1101 unsigned int index = lane->index; in tegra186_usb3_enable_phy_wake() local
1108 value |= SS_PORT_WAKEUP_EVENT(index); in tegra186_usb3_enable_phy_wake()
1115 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index); in tegra186_usb3_enable_phy_wake()
1126 unsigned int index = lane->index; in tegra186_usb3_disable_phy_wake() local
1133 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index); in tegra186_usb3_disable_phy_wake()
1140 value |= SS_PORT_WAKEUP_EVENT(index); in tegra186_usb3_disable_phy_wake()
1151 unsigned int index = lane->index; in tegra186_usb3_phy_remote_wake_detected() local
1155 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index))) in tegra186_usb3_phy_remote_wake_detected()
1183 return tegra_xusb_find_lane(port->padctl, "usb3", port->index); in tegra186_usb3_port_map()
1200 unsigned int index = lane->index; in tegra186_usb3_phy_power_on() local
1204 port = tegra_xusb_find_usb3_port(padctl, index); in tegra186_usb3_phy_power_on()
1206 dev_err(dev, "no port found for USB3 lane %u\n", index); in tegra186_usb3_phy_power_on()
1213 index); in tegra186_usb3_phy_power_on()
1220 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index)); in tegra186_usb3_phy_power_on()
1223 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index)); in tegra186_usb3_phy_power_on()
1225 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index)); in tegra186_usb3_phy_power_on()
1227 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index)); in tegra186_usb3_phy_power_on()
1229 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index)); in tegra186_usb3_phy_power_on()
1236 PORTX_SPEED_SUPPORT_SHIFT(index)); in tegra186_usb3_phy_power_on()
1238 PORTX_SPEED_SUPPORT_SHIFT(index)); in tegra186_usb3_phy_power_on()
1243 value &= ~SSPX_ELPG_VCORE_DOWN(index); in tegra186_usb3_phy_power_on()
1249 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra186_usb3_phy_power_on()
1255 value &= ~SSPX_ELPG_CLAMP_EN(index); in tegra186_usb3_phy_power_on()
1268 unsigned int index = lane->index; in tegra186_usb3_phy_power_off() local
1272 port = tegra_xusb_find_usb3_port(padctl, index); in tegra186_usb3_phy_power_off()
1274 dev_err(dev, "no port found for USB3 lane %u\n", index); in tegra186_usb3_phy_power_off()
1281 value |= SSPX_ELPG_CLAMP_EN_EARLY(index); in tegra186_usb3_phy_power_off()
1287 value |= SSPX_ELPG_CLAMP_EN(index); in tegra186_usb3_phy_power_off()
1293 value |= SSPX_ELPG_VCORE_DOWN(index); in tegra186_usb3_phy_power_off()